EPM9320ABC356-10 vs EPM9320BC356-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ABC356-10 sa pamamagitan ng Altera at EPM9320BC356-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Altera
EPM9320ABC356-10 - MAX 9000 CPLD 6K Gates 320 Macros 356-BGA | Altera
EPM9320ABC356-10 Obsolete
Pagsanggunian na paghahambing
| Parametro | EPM9320ABC356-10 | EPM9320BC356-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX), third-generation | Multiple Array MatriX (MAX) - third generation |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Usable Gates | 6,000 | — |
| Macro Cells | 320 | — |
| Maximum Operating Frequency | 144.9 MHz | — |
| Pin-to-Pin Delay (Speed Grade) | 10 ns | — |
| Supply Voltage (VCC) | 5.0 V | 4.75 V to 5.25 V (5.0 V typical) |
| In-System Programmability (ISP) | Yes, via IEEE 1149.1 JTAG | — |
| Packhaging | 356-pin BGA | 356-ball LBGA (BGA-356, 35x35 mm) |
| Uri ng Pagpapasok | Surface Mount (BGA) | Surface Mount |
| Non-Volatile Configuration | Yes (EEPROM) | — |
| Tindminan RoHS | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: RoHS compliance status] |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature range] | — |
| Macrocells | — | 320 |
| Pin-to-Pin Delay (max) | — | 15 ns |
| In-System Programmability | — | Yes (5.0-V ISP via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 compliant |
| Programmable Type | — | In System Programmable |
| Operating Temperature Grade | — | Commercial |
| Lead-Free | — | [DATA_NEEDED: lead-free status] |