EPM9320ALI84-10 vs EPM9320LC84-10 Comparison
Detailed side-by-side comparison of EPM9320ALI84-10 by Intel and EPM9320LC84-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ALI84-10 | EPM9320LC84-10 |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Family | MAX 9000 | MAX 9000 EPLD |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 to 12,000 | 6000 (typical) |
| Macrocells | 320 | 320 |
| User I/O Pins | 84 | — |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-pin PLCC (JEDEC MO-047) |
| Pin-to-Pin Delay (Tpd1) | 10 ns | — |
| Maximum Counter Frequency | 144 MHz | — |
| Supply Voltage (VCC) | 5.0 V | 5.0 V (typical, see datasheet) |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG | — |
| Program Memory Technology | CMOS EEPROM | — |
| Process Technology | CMOS | 0.7 µm CMOS EEPROM/UV-EPROM |
| Architecture | Multiple Array MatriX (MAX) | — |
| Operating Temperature Range | -40C to +85C (Industrial) | — |
| Mounting Type | Surface Mount (PLCC socket compatible) | Surface Mount (PLCC socket also common) |
| Device | — | EPM9320 |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 168 (varies by package) |
| Pin-to-Pin Logic Delay (tPD) | — | 10 ns |
| Maximum Frequency (fCNT) | — | [DATA_NEEDED: fCNT in MHz] |
| Operating Temperature | — | 0C to +70C (commercial) [DATA_NEEDED: exact grade suffix] |
| Programming Interface | — | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible |
| Configuration | — | Non-volatile EEPROM (instant-on, no boot PROM) |
| RoHS Status | — | ROHS3 Compliant (per fpgalink listing) |
| Moisture Sensitivity Level (MSL) | — | MSL-3, 168 hours (per fpgalink listing) |
| Manufacturer Lead Time | — | 1-7 days (per fpgalink listing) |