EPM9320LC84-10 - MAX 9000 EPLD, 84-PLCC, 10ns | Intel / Altera
MPN: EPM9320LC84-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $96.03 | $96.03 |
| 10 | $93.5 | $935.00 |
| 100 | $92.19 | $9,219.00 |
| 500 | $88.5 | $44,250.00 |
| 1,000 | $84.96 | $84,960.00 |
Drop-in alternatives for EPM9320LC84-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9320LC84-15
β Drop-Inβ In Stock
$17.95 / Unit
View Datasheet βEPM9320ALI84-10
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$19.95 / Unit
View Datasheet βEPM9320ALI84-10N
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$21.95 / Unit
View Datasheet βEPM9320ALC84-10
β Drop-Inβ In Stock
$19.8 / Unit
View Datasheet βEPM9320ALC84-10N
β Drop-Inβ In Stock
$21.4 / Unit
View Datasheet βEPM9320LC84-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 EPLD |
| Device | EPM9320 |
| Macrocells | 320 |
| Usable Gates | 6000 (typical) |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O Pins | 168 (varies by package) |
| Pin-to-Pin Logic Delay (tPD) | 10 ns |
| Supply Voltage (VCC) | 5.0 V (typical, see datasheet) |
| Process Technology | 0.7 Β΅m CMOS EEPROM/UV-EPROM |
| Package | 84-pin PLCC (JEDEC MO-047) |
| Mounting Type | Surface Mount (PLCC socket also common) |
| Programming Interface | JTAG (IEEE 1149.1) boundary-scan, Altera ByteBlaster compatible |
| Configuration | Non-volatile EEPROM (instant-on, no boot PROM) |
| RoHS Status | ROHS3 Compliant (per fpgalink listing) |
| Moisture Sensitivity Level (MSL) | MSL-3, 168 hours (per fpgalink listing) |
| Manufacturer Lead Time | 1-7 days (per fpgalink listing) |
EPM9320LC84-10 Pin Configuration
| Pin 1 | I/O β User I/O pin (function defined by design) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | VCC β 5V supply |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | GND β Ground |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | I/O β User I/O pin |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | VCC β 5V supply |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | I/O β User I/O pin |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | GND β Ground |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | I/O β User I/O pin |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | I/O β User I/O pin |
| Pin 66 | VCC β 5V supply |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | I/O β User I/O pin |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | GND β Ground |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | I/O β User I/O pin |
| Pin 84 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320LC84-10 is suitable for 6 applications: 32-bit Address Decoding for Embedded CPU Boards, ISA / VME Bus Interface Glue Logic, Programmable Keyboard / Video / Mouse Controllers, Industrial PLC and Process Control State Machines, Telecom Line Card Control Logic, Legacy Test and Measurement Instrumentation.
32-bit Address Decoding for Embedded CPU Boards
The EPM9320LC84-10 fits legacy 32-bit CPU address decoding thanks to its 320 macrocells (sufficient for full 24-32 bit address-map decoding with chip-select outputs) and 10 ns tPD, which adds minimal wait-state overhead on 33 MHz ISA/VME-style buses. With 84 pins in a PLCC socket, board designers can map glue logic into a single device instead of cascading 74-series decoders, saving PCB area and improving noise immunity. Unlike SRAM FPGAs, its non-volatile EEPROM configuration boots instantly with no bitstream loader, which is decisive in deterministic-boot industrial controllers. The instant-on behavior also means no external configuration PROM, reducing BOM cost and board complexity. Engineers should budget the 10 ns delay into the bus access cycle to avoid violating the CPU's chip-select setup time.
Recommended
ISA / VME Bus Interface Glue Logic
The EPM9320LC84-10 is a natural fit for ISA and VME bus interfaces where deterministic timing and bus arbitration must be implemented in hardware. Its 168 maximum user I/Os (the 84-PLCC exposes roughly half this count) accommodate bus-control signals, interrupt acknowledge, DMA arbitration, and address/data buffering in one device. The 10 ns tPD supports 8.33 MHz ISA bus cycles without inserting wait states, while the JTAG (IEEE 1149.1) interface simplifies board-level boundary-scan testing. Compared to discrete 74LS/74F glue, the EPLD reduces chip count from 6-10 packages to a single IC, improving reliability and easing EMC compliance. The MAX+PLUS II development environment includes pre-built bus-interface macrofunctions that drop directly into the design.
Recommended
Programmable Keyboard / Video / Mouse Controllers
The EPM9320LC84-10 fits legacy keyboard, video, and mouse controllers in industrial PCs because its 320 macrocells can implement a full PS/2 or AT keyboard scan matrix plus video timing generator plus mouse serial interface in one chip. The 10 ns tPD supports standard VGA 25 MHz pixel-clock prescalers when the design includes simple video sync generation, and the JTAG port allows in-system firmware updates during product maintenance. The 84-pin PLCC socketed package simplifies field replacement in legacy systems where down-time must be minimized. Designers should add external ESD protection on the PS/2 and VGA lines since the EPLD's 5 V CMOS I/O is not rated for direct cable-discharge events. Power consumption is typically under 200 mW at 5 V thanks to the CMOS EEPROM process.
Recommended
Industrial PLC and Process Control State Machines
The EPM9320LC84-10 is widely deployed in industrial PLCs and process controllers where deterministic state-machine execution is required and design qualification cycles span decades. Its 320 macrocells handle multi-state sequential control logic with parallel I/O expansion, and the 10 ns tPD enables sub-microsecond response to safety interrupts. The non-volatile EEPROM configuration ensures the PLC powers up in a known safe state after a brown-out, which is critical for IEC 61508 SIL-rated machinery. Intel (Altera) maintains the MAX 9000 family specifically for long-lifecycle industrial customers, with many PLC vendors standardizing on PLCC-84 sockets for easy field replacement. Industrial temperature variants such as EPM9320ALI84-10 extend operation to -40C to +85C for outdoor cabinets.
Recommended
Telecom Line Card Control Logic
The EPM9320LC84-10 is suitable for telecom line-card glue logic including TDM bus arbitration, HDLC framing pre-processing, and front-panel LED multiplexing. Its 320 macrocells handle T1/E1 frame alignment plus per-channel signaling extraction, and the 10 ns tPD accommodates 8 kHz to 2.048 MHz PCM bus rates without buffering. The JTAG interface allows in-system programming during board bring-up, while the non-volatile configuration eliminates the bitstream-loader overhead required by SRAM FPGAs. Telecom line cards typically operate from -40C to +85C, so the industrial-temperature EPM9320ALI84-10 is the preferred variant in this application. Long-term availability is supported by Intel's industrial-grade product longevity program for telecom customers.
Recommended
Legacy Test and Measurement Instrumentation
The EPM9320LC84-10 fits legacy digital-storage oscilloscopes, logic analyzers, and bench-top instruments where the instrument's hardware design was qualified years ago and parts must be sourced for ongoing production and repair. Its 320 macrocells implement front-panel key-scan matrices, LCD/CRT timing, trigger logic, and parallel data acquisition sequencing. The 10 ns tPD is fast enough for 100 MHz trigger comparators and 50 MHz state-machine sequencing. PLCC-84 sockets are field-serviceable, allowing technicians to swap the EPLD without re-flowing the board, which is essential for legacy instrument field repair. The non-volatile EEPROM boot ensures the instrument powers up to a calibrated default state without operator intervention.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320LC84-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320LC84-15 | EPM9320ALI84-10 | EPM9320ALI84-10N | EPM9320ALC84-10 | EPM9320ALC84-10N |
|---|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | 84-pin PLCC | 84-pin PLCC (same) | 84-pin PLCC (same) | 84-pin PLCC (same) | 84-pin PLCC (same) | 84-pin PLCC (same) |
| Macrocells | 320 | 320 (same) | 320 (same) | 320 (same) | 320 (same) | 320 (same) |
| Pin-to-Pin Delay (tPD) | 10 ns | 15 ns (-50% slower) | 10 ns (same) | 10 ns (same) | 10 ns (same) | 10 ns (same) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) | -40C to +85C (industrial) | -40C to +85C (industrial) | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Lead-Free / RoHS | ROHS3 Compliant | [DATA_NEEDED] | [DATA_NEEDED] | Yes (lead-free) | Yes (lead-free) | Yes (lead-free) |
| Lifecycle Status | NRND | NRND | NRND | NRND | NRND | NRND |
| Configuration Memory | Non-volatile EEPROM | Non-volatile EEPROM (same) | Non-volatile EEPROM (same) | Non-volatile EEPROM (same) | Non-volatile EEPROM (same) | Non-volatile EEPROM (same) |
Key Differentiators
- 10 ns speed grade in PLCC-84 - best balance of speed and legacy availability (vs EPM9320LC84-15)
- Industrial temperature grade option in same PLCC-84 footprint (vs EPM9320ALI84-10)
- Non-volatile EEPROM boot - no configuration PROM required (vs SRAM-based FPGAs (e.g. Cyclone, Spartan))
Design Notes
Estimated: the EPM9320LC84-10 has four VCC pins (22, 44, 66 and a fourth supply pin typically tied to VCCIO) and four GND pins (11, 33, 55, 77) distributed around the 84-PLCC package. Place at least one 0.1 uF decoupling capacitor adjacent to each VCC pin and a 10 uF bulk tantalum or ceramic capacitor at the package corner. The four ground pins should be tied to a single ground plane with short, wide traces to minimize ground bounce on high-speed 10 ns outputs.
The 10 ns tPD edge rates produce significant harmonics up to 50 MHz. Route all MAX 9000 outputs with controlled-impedance traces (typically 50 ohm microstrip) and avoid parallel runs longer than 25 mm to suppress crosstalk. Unused I/O pins must be programmed as outputs and tied to ground (or defined as inputs with weak pull-ups enabled) per MAX+PLUS II default settings, otherwise floating inputs cause ICC current spikes during transitions.
Critical: the EPM9320LC84-10 is NRND and most current inventory is from independent distributors. Always verify the date code, lot trace, and ask for a C-of-C (Certificate of Conformance) before placing parts into production. Counterfeit risk is elevated for legacy Altera MAX 9000 parts. For new designs, evaluate MAX II (EPM240/EPM570) or MAX V CPLDs in TQFP packages - they are still active, cheaper, and offer higher macrocell counts.
Compliance Information
ROHS3 compliant per fpgalink distributor listing. Lead-free per modern Intel/Altera material declaration. REACH status not explicitly stated - assumed compliant for legacy Altera parts. AEC-Q100 not applicable (industrial/aerospace qualification, not automotive). Conflict-mineral reporting compliant per Intel's annual CMRT filing.
