EPM9320ALI84-10 vs EPM9320LI84-20N Comparison
Detailed side-by-side comparison of EPM9320ALI84-10 by Intel and EPM9320LI84-20N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ALI84-10 | EPM9320LI84-20N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Usable Gates | 6,000 to 12,000 | 6,000 to 12,000 |
| Macrocells | 320 | 320 |
| User I/O Pins | 84 | 60 |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Pin-to-Pin Delay (Tpd1) | 10 ns | — |
| Maximum Counter Frequency | 144 MHz | 118 MHz |
| Supply Voltage (VCC) | 5.0 V | — |
| In-System Programmability | Yes, via IEEE 1149.1 JTAG | — |
| Program Memory Technology | CMOS EEPROM | — |
| Process Technology | CMOS | Advanced CMOS EEPROM |
| Architecture | Multiple Array MatriX (MAX) | Multiple Array MatriX (MAX) - third generation |
| Operating Temperature Range | -40C to +85C (Industrial) | — |
| Mounting Type | Surface Mount (PLCC socket compatible) | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Total Pins | — | 84 |
| Propagation Delay (tPD) | — | 20 ns (speed grade -20) |
| Pin-to-Pin Delay | — | 16 ns (per DigChip spec block) |
| Logic Family | — | CMOS, EEPROM-based |
| Supply Voltage | — | 5.0 V |
| Operating Temperature | — | 0 C to +70 C (commercial) |
| Programming Interface | — | IEEE 1149.1 JTAG, in-system programmable |
| RoHS Status | — | [DATA_NEEDED: RoHS compliance status] |