EPM9320LI84-20N - MAX 9000 CPLD, 320 Macrocells, 84-PLCC | Altera
MPN: EPM9320LI84-20N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $18.5 | $18.50 |
| 10 | $16.2 | $162.00 |
| 100 | $13.85 | $1,385.00 |
| 500 | $11.4 | $5,700.00 |
| 1,000 | $9.75 | $9,750.00 |
Drop-in alternatives for EPM9320LI84-20N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9320LC84-20N
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View Datasheet →EPM9320LC84-20
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View Datasheet →EPM9320LC84-15
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View Datasheet →EPM9320LC84-10
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View Datasheet →EPM9320ALC84-20
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View Datasheet →EPM9320ALI84-10
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View Datasheet →EPM9320ALI84-10N
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$21.95 / Unit
View Datasheet →EPM9320LI84-20N Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 |
| Usable Gates | 6,000 to 12,000 |
| User I/O Pins | 60 |
| Total Pins | 84 |
| Package | PLCC-84 (Plastic Leaded Chip Carrier, J-lead) |
| Propagation Delay (tPD) | 20 ns (speed grade -20) |
| Pin-to-Pin Delay | 16 ns (per DigChip spec block) |
| Maximum Counter Frequency | 118 MHz |
| Logic Family | CMOS, EEPROM-based |
| Supply Voltage | 5.0 V |
| Operating Temperature | 0 C to +70 C (commercial) |
| Programming Interface | IEEE 1149.1 JTAG, in-system programmable |
| Architecture | Multiple Array MatriX (MAX) - third generation |
| Process Technology | Advanced CMOS EEPROM |
EPM9320LI84-20N Pin Configuration
| Pin 1 | I/O — User I/O (bank-dependent assignment per datasheet) |
| Pin 2 | I/O — User I/O |
| Pin 3 | I/O — User I/O |
| Pin 4 | I/O — User I/O |
| Pin 5 | I/O — User I/O |
| Pin 6 | I/O — User I/O |
| Pin 7 | I/O — User I/O |
| Pin 8 | I/O — User I/O |
| Pin 9 | I/O — User I/O |
| Pin 10 | I/O — User I/O |
| Pin 11 | GND — Ground |
| Pin 12 | I/O — User I/O |
| Pin 13 | I/O — User I/O |
| Pin 14 | I/O — User I/O |
| Pin 15 | I/O — User I/O |
| Pin 16 | I/O — User I/O |
| Pin 17 | I/O — User I/O |
| Pin 18 | I/O — User I/O |
| Pin 19 | I/O — User I/O |
| Pin 20 | I/O — User I/O |
| Pin 21 | I/O — User I/O |
| Pin 22 | I/O — User I/O |
| Pin 23 | I/O — User I/O |
| Pin 24 | GND — Ground |
| Pin 25 | TDI — JTAG Test Data In |
| Pin 26 | TMS — JTAG Test Mode Select |
| Pin 27 | TCK — JTAG Test Clock |
| Pin 28 | TRST — JTAG Test Reset (active low) |
| Pin 29 | TDO — JTAG Test Data Out |
| Pin 30 | I/O — User I/O |
| Pin 31 | GND — Ground |
| Pin 32 | I/O — User I/O |
| Pin 33 | I/O — User I/O |
| Pin 34 | I/O — User I/O |
| Pin 35 | I/O — User I/O |
| Pin 36 | I/O — User I/O |
| Pin 37 | I/O — User I/O |
| Pin 38 | I/O — User I/O |
| Pin 39 | I/O — User I/O |
| Pin 40 | I/O — User I/O |
| Pin 41 | I/O — User I/O |
| Pin 42 | VCC — +5.0V supply |
| Pin 43 | I/O — User I/O |
| Pin 44 | I/O — User I/O |
| Pin 45 | I/O — User I/O |
| Pin 46 | I/O — User I/O |
| Pin 47 | I/O — User I/O |
| Pin 48 | I/O — User I/O |
| Pin 49 | I/O — User I/O |
| Pin 50 | I/O — User I/O |
| Pin 51 | I/O — User I/O |
| Pin 52 | I/O — User I/O |
| Pin 53 | I/O — User I/O |
| Pin 54 | I/O — User I/O |
| Pin 55 | I/O — User I/O |
| Pin 56 | GND — Ground |
| Pin 57 | I/O — User I/O |
| Pin 58 | I/O — User I/O |
| Pin 59 | I/O — User I/O |
| Pin 60 | I/O — User I/O |
| Pin 61 | I/O — User I/O |
| Pin 62 | I/O — User I/O |
| Pin 63 | I/O — User I/O |
| Pin 64 | I/O — User I/O |
| Pin 65 | I/O — User I/O |
| Pin 66 | I/O — User I/O |
| Pin 67 | I/O — User I/O |
| Pin 68 | VCC — +5.0V supply |
| Pin 69 | I/O — User I/O |
| Pin 70 | I/O — User I/O |
| Pin 71 | I/O — User I/O |
| Pin 72 | I/O — User I/O |
| Pin 73 | I/O — User I/O |
| Pin 74 | I/O — User I/O |
| Pin 75 | I/O — User I/O |
| Pin 76 | I/O — User I/O |
| Pin 77 | I/O — User I/O |
| Pin 78 | I/O — User I/O |
| Pin 79 | I/O — User I/O |
| Pin 80 | I/O — User I/O |
| Pin 81 | GND — Ground |
| Pin 82 | I/O — User I/O |
| Pin 83 | I/O — User I/O |
| Pin 84 | I/O — User I/O |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320LI84-20N is suitable for 6 applications: Microprocessor Bus Interface Glue Logic, Peripheral Controller and State-Machine Implementation, Industrial Control and Factory Automation, Legacy Board Repair and Footprint-Compatible Upgrade, JTAG Boundary-Scan and Test Infrastructure, Telecom Backplane Glue Logic.
Microprocessor Bus Interface Glue Logic
The EPM9320LI84-20N serves as a high-density address decoder, chip-select generator, and wait-state controller for 8/16/32-bit microprocessor systems. With 320 macrocells and 60 user I/Os, it can replace multiple discrete 22V10, PAL, and GAL devices on legacy ISA, VME, or proprietary bus backplanes. The 20 ns pin-to-pin delay fits one 25 MHz bus cycle with comfortable margin, and the deterministic MAX 9000 timing model eliminates the static-timing-analysis complexity of FPGA-based solutions. Place the CPLD adjacent to the CPU/ASIC with short, impedance-controlled traces to the address and data bus, and use the JTAG port for in-system reprogramming during board bring-up.
Recommended
Peripheral Controller and State-Machine Implementation
Designers use the EPM9320LI84-20N to consolidate multi-chip TTL state machines, sequencers, and peripheral controllers into a single non-volatile device. The 320-macrocell capacity accommodates 30-40 typical state machines with deep encoding, and the EEPROM-backed configuration means the device wakes up instantly at power-up with no FPGA-style configuration latency - critical for systems that must respond to interrupts before any firmware initializes. Typical use cases include floppy-disk controllers, SCSI sequencers, and legacy industrial protocol engines. Pair with a 5.0-V microcontroller such as the 8051 family or a VMEbus master for tightly-coupled control loops.
Recommended
Industrial Control and Factory Automation
In industrial control backplanes and PLC I/O modules, the EPM9320LI84-20N provides deterministic glue logic between sensors, optocouplers, and the central controller. Its 60 user I/Os accommodate 32-48 digital I/O channels per device, and the 0 C to +70 C commercial operating range fits enclosed cabinet environments. Designers value the in-system programmability for field firmware updates without removing the module, and the non-volatile EEPROM for instant-on behavior after power-cycle events common in factory environments. Provide robust 5.0-V supply decoupling (10 uF + 0.1 uF per VCC pin) to ride through industrial transients.
Recommended
Legacy Board Repair and Footprint-Compatible Upgrade
The primary modern use case for the EPM9320LI84-20N is exact-footprint replacement of failed MAX 9000 CPLDs on legacy boards still in service across telecom, aerospace, military, and industrial segments. Because the device uses an industry-standard 84-pin PLCC J-lead socket (1.27 mm pitch, 30.35 mm body), sockets allow swap-out without PCB rework. Engineers sourcing replacements should request factory-original date code to avoid counterfeit risk, and verify the JTAG IDCODE matches the Altera MAX 9000 family signature before re-programming. For capacity upgrades in the same socket, the EPM9320LC84-15 (-15 speed grade) provides a 25% timing improvement without any footprint change.
Recommended
JTAG Boundary-Scan and Test Infrastructure
The EPM9320LI84-20N supports IEEE 1149.1 JTAG boundary-scan with dedicated TMS, TCK, TDO, TDI, and TRST pins, enabling integration into board-level boundary-scan test architectures (per JTAG 1149.1 and 1149.6 standards). On complex multi-layer boards with high-density BGAs and limited physical probe access, the CPLD's boundary-scan chain provides virtual access to inter-board interconnect for manufacturing test and field diagnostics. The 20 ns propagation delay does not impact JTAG TCK rates up to 10 MHz, which is adequate for most production testers. Combine with other JTAG-compliant devices in a daisy-chain configuration for full board test coverage.
Recommended
Telecom Backplane Glue Logic
In telecom equipment such as legacy TDM switches, cross-connects, and central-office line cards, the EPM9320LI84-20N provides high-density bus arbitration, interrupt prioritization, and timing-reference distribution. The deterministic 20 ns timing model supports T1/E1 framer interfaces at 1.544/2.048 MHz and HDB3 line coding with comfortable margin. The 60 user I/Os handle full 8-bit TDM buses plus framing and clock distribution in a single device. The EEPROM-backed configuration enables rapid field-recovery after central-office power events without manual intervention. For new telecom designs, FPGAs or ASSPs have largely displaced this use case.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320LI84-20N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320LC84-20N | EPM9320LC84-20 | EPM9320LC84-15 | EPM9320LC84-10 | EPM9320ALI84-10N |
|---|---|---|---|---|---|---|
| Package | PLCC-84 (J-lead) | PLCC-84 (J-lead) - same | PLCC-84 (J-lead) - same | PLCC-84 (J-lead) - same | PLCC-84 (J-lead) - same | PLCC-84 (J-lead) - same |
| Brand | Altera | Altera | Altera | Altera | Altera | Altera |
| Speed Grade | -20 | -20 | -15 | -10 | -10 | |
| Pin-to-Pin Delay | 20 ns | 20 ns | 15 ns | 10 ns | 10 ns | |
| Macrocells | 320 | 320 | 320 | 320 | 320 | |
| User I/Os | 60 | 60 | 60 | 60 | 60 | |
| Operating Temperature | 0 C to +70 C (commercial, I-suffix) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | ||
| Programming Interface | JTAG IEEE 1149.1, in-system | JTAG IEEE 1149.1, in-system | JTAG IEEE 1149.1, in-system | JTAG IEEE 1149.1, in-system | ||
| Pb-Free Finish (N-suffix) | Yes | Yes | No (SnPb) | No (SnPb) |
Key Differentiators
- Largest-density member of the MAX 9000 family with 320 macrocells (vs EPM9320ALI84-10N)
- Pb-free (N-suffix) finish for RoHS-compliant assembly (vs EPM9320LC84-20)
- Industrial-temp-grade silicon baseline (I-suffix) (vs EPM9320LC84-20N)
Design Notes
Use a high-quality PLCC-84 socket (e.g., 3M Textool or equivalent machine-pin socket) rather than soldering the device directly to the PCB. This enables rapid swap-out for legacy-board repair and protects against thermal exposure during rework. For production boards that must solder the CPLD directly, follow JEDEC J-STD-020 reflow profile for the Pb-free N-suffix variant; legacy SnPb-finished parts use the SnPb profile with peak temperature of 220 C.
Place one 0.1 uF X7R ceramic decoupling capacitor adjacent to each VCC pin (pins 42 and 68 per the PLCC-84 pinout) and a 10 uF tantalum or aluminum polymer bulk capacitor at the PLCC socket entry point. The MAX 9000 family draws peak current during JTAG programming and concurrent-output switching events; bulk decoupling prevents supply collapse during in-system reconfiguration. Estimated: typical ICC at 5.0 V with all I/Os switching is approximately 200-300 mA; transient peaks may reach 500 mA during programming.
Verify the JTAG IDCODE matches the Altera MAX 9000 family signature (manufacturer ID 0x0110, device ID per datasheet) before programming. Counterfeit MAX 9000 parts with mismatched IDCODEs have been documented in the secondary market; use only authorized Altera/Intel distributors or factory-tray direct orders. For boundary-scan chain debugging, ensure the TRST pin (pin 28) is pulled high through a 10 kohm resistor per JTAG 1149.1 - floating TRST can cause false JTAG state transitions on power-up.
Route the JTAG TCK signal as a 50 ohm controlled-impedance trace with series-termination at the driver; keep TCK trace length under 50 mm if possible and isolate it from fast-edge I/O signals. For boards with multiple JTAG devices, use star-routing from a JTAG controller header rather than daisy-chain to minimize reflections on TCK. The 20 ns MAX 9000 propagation delay is not impacted by JTAG TCK rates up to 10 MHz, but signal-integrity issues can corrupt the JTAG state machine.
Compliance Information
N-suffix indicates Pb-free finish per Altera legacy naming convention. RoHS compliance inferred from N-suffix Pb-free finish; full declaration not present in supplied data. AEC-Q100 not applicable to CPLDs in commercial temperature range.
