EPM9320ARC208-10 vs EPM9320RC208-15N Comparison
Detailed side-by-side comparison of EPM9320ARC208-10 by Altera and EPM9320RC208-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ARC208-10 | EPM9320RC208-15N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Last Time Buy | NRND |
| Device Family | MAX 9000 | — |
| Product Type | CPLD (Complex Programmable Logic Device) | — |
| Macrocells | 320 | — |
| Usable Gates | 6,000 | 6,000 |
| Pin-to-Pin Delay (tPD) | 10 ns | — |
| Maximum Frequency | 144.9 MHz | — |
| Supply Voltage | 5.0 V | 5.0 V |
| Logic Blocks (LABs) | 16 | — |
| Programmability | EEPROM, in-system programmable via JTAG | — |
| JTAG Support | IEEE Std. 1149.1 compliant | — |
| Speed/Power Optimization | Per-macrocell programmable, 50% power mode available | — |
| Package | RQFP-208 (Power Quad Flat Pack) | 208-pin RQFP (PowerQuad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | — |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: RoHS status] |
| Family | — | MAX 9000 |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macro Cells | — | 320 |
| Flip-Flops | — | 484 |
| Configurable I/O Lines | — | 128 |
| Propagation Delay (tPD) | — | 15 ns |
| Maximum Clock Frequency | — | 117.6 MHz |
| I/O Voltage Compatibility | — | 3.3 V or 5 V |
| Configuration Technology | — | CMOS EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Terminal Pitch | — | 0.5 mm |
| Operating Temperature Range | — | 0C to +70C (commercial) |
| Packaging | — | Tray |