EPM9320ARC208-10N vs EPM9320RC208-15 Comparison
Detailed side-by-side comparison of EPM9320ARC208-10N by Altera and EPM9320RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320ARC208-10N | EPM9320RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 320 | 320 |
| Logic Gates | 6,000 gates | — |
| Logic Array Blocks (LABs) | 16 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 144.9 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| User I/O Pins | 168 | — |
| Dedicated Input Pins | 12 | — |
| Package | 208-pin RQFP (BFQFP with exposed pad) | 208-pin RQFP (Power QFP) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0C to +70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Interface | IEEE Std. 1149.1 JTAG | — |
| Configuration Memory | Non-volatile EEPROM | — |
| RoHS Status | Compliant (lead-free 'N' suffix) | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 9000 |
| Usable Gates | — | 6,000 |
| Pin-to-Pin Propagation Delay | — | 15 ns (speed grade -15) |
| Maximum Clock Frequency | — | 117.6 MHz |
| Supply Voltage | — | 5.0 V |
| Configuration Technology | — | EEPROM-based (non-volatile) |
| In-System Programmability | — | Yes (ISP via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Package Type | — | 208-BFQFP Exposed Pad |
| Number of I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Logic Array Blocks | — | [DATA_NEEDED: LAB count] |
| Lifecycle Status | — | Obsolete (PDN0706, 2007) |