EPM9320ARC208-10N vs EPM9320RC208-15 Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9320ARC208-10N sa pamamagitan ng Altera at EPM9320RC208-15 sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9320ARC208-10N | EPM9320RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | CPLD (Complex Programmable Logic Device) | — |
| Macro Cells | 320 | 320 |
| Logic Gates | 6,000 gates | — |
| Logic Array Blocks (LABs) | 16 | — |
| Propagation Delay (tPD) | 10 ns | — |
| Maximum Frequency | 144.9 MHz | — |
| Supply Voltage (VCC) | 5 V | — |
| User I/O Pins | 168 | — |
| Dedicated Input Pins | 12 | — |
| Packhaging | 208-pin RQFP (BFQFP with exposed pad) | 208-pin RQFP (Power QFP) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Temperature na Operasyon | 0C to +70C (Commercial) | [DATA_NEEDED: operating temperature range] |
| Programming Interface | IEEE Std. 1149.1 JTAG | — |
| Configuration Memory | Non-volatile EEPROM | — |
| Tindminan RoHS | Compliant (lead-free 'N' suffix) | [DATA_NEEDED: RoHS status] |
| Device Family | — | MAX 9000 |
| Usable Gates | — | 6,000 |
| Pin-to-Pin Propagation Delay | — | 15 ns (speed grade -15) |
| Maksimum na Taktiko ng Oras | — | 117.6 MHz |
| Volte ng Pagbibigay | — | 5.0 V |
| Configuration Technology | — | EEPROM-based (non-volatile) |
| In-System Programmability | — | Yes (ISP via JTAG) |
| JTAG Interface | — | IEEE Std. 1149.1 |
| Package Type | — | 208-BFQFP Exposed Pad |
| Number of I/O Pins | — | [DATA_NEEDED: user I/O count] |
| Logic Array Blocks | — | [DATA_NEEDED: LAB count] |
| Katayuan ng Lifecycle | — | Obsolete (PDN0706, 2007) |