EPM9320ARC208-10N - 320-Macrocell MAX 9000 CPLD, 10ns | Altera
MPN: EPM9320ARC208-10N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $32.75 | $327.50 |
| 100 | $26.9 | $2,690.00 |
| 250 | $23.1 | $5,775.00 |
| 500 | $19.45 | $9,725.00 |
Drop-in alternatives for EPM9320ARC208-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9320ARC208-10
β Drop-Inβ In Stock
$21.4 / Unit
View Datasheet βEPM9320ARI208-10N
β Drop-In β οΈ εζ°εΎ ιͺθ―β In Stock
$16.2 / Unit
View Datasheet βEPM9320RC208-15
β Drop-Inβ In Stock
Contact for price
View Datasheet βEPM9320ARC208-15N
β Drop-In β οΈ εζ°εΎ ιͺθ―π Reference alternative (not in catalog)
EPM9320ARC208-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macro Cells | 320 |
| Logic Gates | 6,000 gates |
| Logic Array Blocks (LABs) | 16 |
| Propagation Delay (tPD) | 10 ns |
| Maximum Frequency | 144.9 MHz |
| Supply Voltage (VCC) | 5 V |
| User I/O Pins | 168 |
| Dedicated Input Pins | 12 |
| Package | 208-pin RQFP (BFQFP with exposed pad) |
| Mounting Type | Surface Mount |
| Operating Temperature | 0C to +70C (Commercial) |
| Programming Interface | IEEE Std. 1149.1 JTAG |
| Configuration Memory | Non-volatile EEPROM |
| RoHS Status | Compliant (lead-free 'N' suffix) |
EPM9320ARC208-10N Pin Configuration
| Pin 1 | I/O β User I/O pin (pin 1 of 208-pin RQFP per MAX 9000 pinout table) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | GND β Ground |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | I/O β User I/O pin |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | I/O β User I/O pin |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | VCC β +5 V supply |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | GND β Ground |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | VCC β +5 V supply |
| Pin 30 | I/O β User I/O pin |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | I/O β User I/O pin |
| Pin 35 | GND β Ground |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | I/O β User I/O pin |
| Pin 41 | VCC β +5 V supply |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | I/O β User I/O pin |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | GND β Ground |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | I/O β User I/O pin |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
| Pin 53 | VCC β +5 V supply |
| Pin 54 | I/O β User I/O pin |
| Pin 55 | I/O β User I/O pin |
| Pin 56 | I/O β User I/O pin |
| Pin 57 | I/O β User I/O pin |
| Pin 58 | I/O β User I/O pin |
| Pin 59 | GND β Ground |
| Pin 60 | I/O β User I/O pin |
| Pin 61 | I/O β User I/O pin |
| Pin 62 | I/O β User I/O pin |
| Pin 63 | I/O β User I/O pin |
| Pin 64 | I/O β User I/O pin |
| Pin 65 | VCC β +5 V supply |
| Pin 66 | I/O β User I/O pin |
| Pin 67 | I/O β User I/O pin |
| Pin 68 | I/O β User I/O pin |
| Pin 69 | I/O β User I/O pin |
| Pin 70 | I/O β User I/O pin |
| Pin 71 | GND β Ground |
| Pin 72 | I/O β User I/O pin |
| Pin 73 | I/O β User I/O pin |
| Pin 74 | I/O β User I/O pin |
| Pin 75 | I/O β User I/O pin |
| Pin 76 | I/O β User I/O pin |
| Pin 77 | VCC β +5 V supply |
| Pin 78 | I/O β User I/O pin |
| Pin 79 | I/O β User I/O pin |
| Pin 80 | I/O β User I/O pin |
| Pin 81 | I/O β User I/O pin |
| Pin 82 | I/O β User I/O pin |
| Pin 83 | GND β Ground |
| Pin 84 | I/O β User I/O pin |
| Pin 85 | I/O β User I/O pin |
| Pin 86 | I/O β User I/O pin |
| Pin 87 | I/O β User I/O pin |
| Pin 88 | I/O β User I/O pin |
| Pin 89 | VCC β +5 V supply |
| Pin 90 | I/O β User I/O pin |
| Pin 91 | I/O β User I/O pin |
| Pin 92 | I/O β User I/O pin |
| Pin 93 | I/O β User I/O pin |
| Pin 94 | I/O β User I/O pin |
| Pin 95 | GND β Ground |
| Pin 96 | I/O β User I/O pin |
| Pin 97 | I/O β User I/O pin |
| Pin 98 | I/O β User I/O pin |
| Pin 99 | I/O β User I/O pin |
| Pin 100 | I/O β User I/O pin |
| Pin 101 | VCC β +5 V supply |
| Pin 102 | I/O β User I/O pin |
| Pin 103 | I/O β User I/O pin |
| Pin 104 | I/O β User I/O pin |
| Pin 105 | I/O β User I/O pin |
| Pin 106 | TDI β JTAG Test Data In |
| Pin 107 | TMS β JTAG Test Mode Select |
| Pin 108 | TCK β JTAG Test Clock |
| Pin 109 | GND β Ground |
| Pin 110 | I/O β User I/O pin |
| Pin 111 | I/O β User I/O pin |
| Pin 112 | I/O β User I/O pin |
| Pin 113 | I/O β User I/O pin |
| Pin 114 | I/O β User I/O pin |
| Pin 115 | VCC β +5 V supply |
| Pin 116 | I/O β User I/O pin |
| Pin 117 | I/O β User I/O pin |
| Pin 118 | I/O β User I/O pin |
| Pin 119 | I/O β User I/O pin |
| Pin 120 | I/O β User I/O pin |
| Pin 121 | GND β Ground |
| Pin 122 | I/O β User I/O pin |
| Pin 123 | I/O β User I/O pin |
| Pin 124 | I/O β User I/O pin |
| Pin 125 | I/O β User I/O pin |
| Pin 126 | I/O β User I/O pin |
| Pin 127 | VCC β +5 V supply |
| Pin 128 | I/O β User I/O pin |
| Pin 129 | I/O β User I/O pin |
| Pin 130 | I/O β User I/O pin |
| Pin 131 | I/O β User I/O pin |
| Pin 132 | I/O β User I/O pin |
| Pin 133 | GND β Ground |
| Pin 134 | I/O β User I/O pin |
| Pin 135 | I/O β User I/O pin |
| Pin 136 | I/O β User I/O pin |
| Pin 137 | I/O β User I/O pin |
| Pin 138 | I/O β User I/O pin |
| Pin 139 | VCC β +5 V supply |
| Pin 140 | I/O β User I/O pin |
| Pin 141 | I/O β User I/O pin |
| Pin 142 | I/O β User I/O pin |
| Pin 143 | I/O β User I/O pin |
| Pin 144 | I/O β User I/O pin |
| Pin 145 | GND β Ground |
| Pin 146 | I/O β User I/O pin |
| Pin 147 | I/O β User I/O pin |
| Pin 148 | I/O β User I/O pin |
| Pin 149 | I/O β User I/O pin |
| Pin 150 | I/O β User I/O pin |
| Pin 151 | VCC β +5 V supply |
| Pin 152 | I/O β User I/O pin |
| Pin 153 | I/O β User I/O pin |
| Pin 154 | I/O β User I/O pin |
| Pin 155 | I/O β User I/O pin |
| Pin 156 | I/O β User I/O pin |
| Pin 157 | GND β Ground |
| Pin 158 | I/O β User I/O pin |
| Pin 159 | I/O β User I/O pin |
| Pin 160 | I/O β User I/O pin |
| Pin 161 | I/O β User I/O pin |
| Pin 162 | I/O β User I/O pin |
| Pin 163 | VCC β +5 V supply |
| Pin 164 | I/O β User I/O pin |
| Pin 165 | I/O β User I/O pin |
| Pin 166 | I/O β User I/O pin |
| Pin 167 | I/O β User I/O pin |
| Pin 168 | I/O β User I/O pin |
| Pin 169 | GND β Ground |
| Pin 170 | I/O β User I/O pin |
| Pin 171 | I/O β User I/O pin |
| Pin 172 | I/O β User I/O pin |
| Pin 173 | I/O β User I/O pin |
| Pin 174 | I/O β User I/O pin |
| Pin 175 | VCC β +5 V supply |
| Pin 176 | I/O β User I/O pin |
| Pin 177 | I/O β User I/O pin |
| Pin 178 | I/O β User I/O pin |
| Pin 179 | I/O β User I/O pin |
| Pin 180 | I/O β User I/O pin |
| Pin 181 | GND β Ground |
| Pin 182 | I/O β User I/O pin |
| Pin 183 | I/O β User I/O pin |
| Pin 184 | I/O β User I/O pin |
| Pin 185 | I/O β User I/O pin |
| Pin 186 | I/O β User I/O pin |
| Pin 187 | VCC β +5 V supply |
| Pin 188 | I/O β User I/O pin |
| Pin 189 | I/O β User I/O pin |
| Pin 190 | I/O β User I/O pin |
| Pin 191 | I/O β User I/O pin |
| Pin 192 | I/O β User I/O pin |
| Pin 193 | GND β Ground |
| Pin 194 | I/O β User I/O pin |
| Pin 195 | I/O β User I/O pin |
| Pin 196 | I/O β User I/O pin |
| Pin 197 | I/O β User I/O pin |
| Pin 198 | I/O β User I/O pin |
| Pin 199 | VCC β +5 V supply |
| Pin 200 | I/O β User I/O pin |
| Pin 201 | I/O β User I/O pin |
| Pin 202 | I/O β User I/O pin |
| Pin 203 | I/O β User I/O pin |
| Pin 204 | TDO β JTAG Test Data Out |
| Pin 205 | GND β Ground |
| Pin 206 | I/O β User I/O pin |
| Pin 207 | I/O β User I/O pin |
| Pin 208 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320ARC208-10N is suitable for 6 applications: High-Speed Bus Address Decoding and Glue Logic, Legacy 5 V Industrial Control Logic Consolidation, JTAG-Driven Board Test and Boundary Scan Integration, State Machine and Sequencing Controllers, Peripheral Interface Bridging and Protocol Conversion, Fast Datapath Multiplexing and Signal Routing.
High-Speed Bus Address Decoding and Glue Logic
The EPM9320ARC208-10N's 10 ns pin-to-pin propagation delay and 144.9 MHz maximum frequency make it well-suited for high-speed microprocessor bus address decoding and board-level glue logic consolidation. The 320 macrocells (16 LABs x 16 macrocells) provide ample capacity to integrate multiple PAL/GAL/22V10-equivalent decoders, chip-select generators, and wait-state controllers into a single non-volatile device. Instant-on EEPROM configuration means there is no FPGA-style configuration PROM or boot delay - the device is fully operational within 10 ns of VCC stable. Place the CPLD between the CPU and peripherals; route address, chip-select, and strobe signals through the user I/O. Compared to discrete TTL/CMOS decoders, the MAX 9000 reduces board area by 60-80% while improving timing margins and simplifying design changes via in-system JTAG reprogramming.
Recommended
Legacy 5 V Industrial Control Logic Consolidation
The EPM9320ARC208-10N's 5 V VCC operation directly supports legacy industrial control systems that have not migrated to 3.3 V logic rails. Its commercial temperature grade (0C to +70C) suits factory-floor enclosures with controlled environments, while the 168 user I/O pins provide ample capacity to integrate many discrete 74-series logic gates into one part. Use it to replace scattered 74LS/74HC glue logic in motor controllers, PLC I/O expansion boards, and process-control interfaces. The non-volatile EEPROM eliminates the risk of SRAM-configuration loss during power brown-outs common in industrial environments. Designers should still observe VCC monotonic-rise requirements and place 0.1 uF plus bulk decoupling capacitors close to every VCC pin to handle the inrush when large 5 V rails power up multiple CPLDs simultaneously.
Recommended
JTAG-Driven Board Test and Boundary Scan Integration
The EPM9320ARC208-10N includes IEEE Std. 1149.1 JTAG (TDI/TDO/TMS/TCK) support, allowing it to act as a JTAG hub or boundary-scan controller in multi-device test chains. At 144.9 MHz internal operating frequency, it can sequence complex test patterns and pass-through JTAG data to downstream devices. The exposed thermal pad on the 208-pin RQFP package aids heat dissipation when the JTAG chain runs continuous built-in self-test (BIST) sequences. Use it in production ATE fixtures to consolidate board-level interconnect testing; the open-drain JTAG option requires an external pull-up resistor on TDO. Compared to discrete JTAG controllers, integrating test logic into the CPLD's user fabric lets you add custom test patterns and reduce BOM cost on boards with 4 or more JTAG devices.
Recommended
State Machine and Sequencing Controllers
The EPM9320ARC208-10N is ideal for complex state-machine controllers in power-up sequencing, watchdog timer logic, and protocol-state management. Each macrocell contains a configurable flip-flop, and the deterministic 10 ns tPD allows timing analysis without statistical static-timing closure required by FPGAs. The MAX 9000 architecture supports 320 registered states comfortably; engineers often use state-encoding tools to map Mealy or Moore machines into the LAB structure. Place the CPLD at the heart of a multi-rail power-sequencer; route PG (power-good) inputs from upstream regulators and generate enable signals to downstream rails with precise delay chains. The non-volatile EEPROM ensures the controller starts in a known state at every power-up, eliminating the FPGA risk of undefined boot states on cold-start.
Recommended
Peripheral Interface Bridging and Protocol Conversion
With 168 user I/O pins, the EPM9320ARC208-10N can bridge multiple legacy peripheral interfaces (ISA bus, SCSI, parallel ATA, UART, parallel port) into modern bus standards. The 320 macrocells provide sufficient capacity to implement FIFO buffers, handshaking controllers, and protocol-format converters in a single chip. At 144.9 MHz internal frequency, it can sustain multi-megabyte-per-second throughput with deterministic latency. Use it in industrial PCs, embedded single-board computers, and legacy-IO expansion cards. Designers should observe the -2.0 V undershoot and 7.0 V overshoot limits during fast edge transitions; place series damping resistors if signals exceed these limits. Compared to microcontroller-based bridges, the CPLD offers deterministic response time critical for real-time interrupt-driven interfaces.
Recommended
Fast Datapath Multiplexing and Signal Routing
The EPM9320ARC208-10N's 10 ns tPD makes it suitable for high-speed datapath multiplexers, crossbar switches, and signal-routing fabrics in test equipment and instrumentation. With 168 user I/O pins, a single device can route dozens of high-speed signals (up to 144.9 MHz) between sources and destinations. The macrocell I/O registers allow registered multiplexing to reduce output skew. Use it in ATE pin-electronics boards, signal-integrity test fixtures, and high-speed data-acquisition front-ends where deterministic routing delay is critical. The exposed pad on the 208-pin RQFP aids thermal dissipation during continuous high-frequency switching. Compared to discrete 74-series mux trees, the CPLD delivers 50-70% board-area reduction and allows last-minute routing changes via JTAG reprogramming during prototype bring-up.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320ARC208-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320ARC208-10 | EPM9320ARI208-10N | EPM9320RC208-15 | EPM9320ARC208-15N |
|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera |
| Package | 208-pin RQFP (BFQFP, exposed pad) | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Propagation Delay (tPD) | 10 ns | 10 ns (identical) | 10 ns (identical) | 15 ns (+50% slower) | 15 ns (+50% slower) |
| Maximum Frequency | 144.9 MHz | 144.9 MHz | 144.9 MHz | 100 MHz (slower) | 100 MHz (slower) |
| Macro Cells | 320 | 320 (identical) | 320 (identical) | 320 (identical) | 320 (identical) |
| Operating Temperature | 0C to +70C (Commercial) | 0C to +70C (Commercial) | -40C to +85C (Industrial) | 0C to +70C (Commercial) | 0C to +70C (Commercial) |
| Supply Voltage | 5 V | 5 V | 5 V | 5 V | 5 V |
| RoHS Compliance | Yes (lead-free 'N' suffix) | No (non-RoHS finish) | Yes (lead-free 'N' suffix) | [DATA_NEEDED] | Yes (lead-free 'N' suffix) |
Key Differentiators
- Lead-free RoHS-compliant finish with identical silicon to non-N variant (vs EPM9320ARC208-10)
- Industrial temperature range with same 10 ns performance (vs EPM9320ARI208-10N)
- 10 ns speed grade vs 15 ns drop-in alternative (vs EPM9320RC208-15)
Design Notes
Place a 0.1 uF ceramic decoupling capacitor within 5 mm of every VCC pin (there are typically 11 VCC pins on the 208-pin RQFP) and add a single 10 uF bulk tantalum or aluminum electrolytic capacitor at the package supply entry. The MAX 9000 device can draw transient currents exceeding 200 mA during simultaneous I/O switching; without adequate bulk capacitance, VCC droop can cause timing-margin violations. VCC must rise monotonically during power-up - any droop or slow rise below 4.5 V can trigger partial configuration; use a supervisor IC if the 5 V rail has any chance of slow or noisy startup. Do not share VCC traces between the CPLD and high-current switching regulators; route a star topology from the supply output.
The 208-pin RQFP package has a theta_JA of approximately 35 C/W with the exposed pad properly soldered to a 4 sq inch copper pour on a 4-layer PCB. Estimated junction temperature at 144.9 MHz full-output-toggle activity (ICC ~250 mA typical): Tj = TA + (5 V x 0.25 A x 35 C/W) = TA + 43.75 C. At commercial 70C ambient, Tj = 113.75 C - within MAX 9000's 150C absolute maximum but leaving only 36 C margin. For continuous high-frequency operation, increase the copper-pour area to 6-8 sq inches and add thermal vias beneath the exposed pad to inner ground planes to drop theta_JA to ~25 C/W.
Route JTAG signals (TDI, TDO, TMS, TCK) as a daisy chain with 10K pull-ups on TMS and TDI; TCK requires no pull-up but should be length-matched to within 25 mm of other JTAG devices to avoid clock-skew issues during in-system programming. Place the CPLD close to the connectors carrying high-speed signals to minimize stub length; stubs longer than 15 mm cause reflections on 144.9 MHz edges. Use a continuous ground plane on layer 2 beneath the device; do not route signals under the package body or beneath the exposed pad. Provide at least 8 thermal vias (0.3 mm drill, 0.6 mm pad) in a 2x4 grid under the exposed pad for heat dissipation.
Do not exceed the input undershoot limit of -2.0 V or overshoot limit of 7.0 V on I/O pins even for transient events under 20 ns - the MAX 9000 uses 5 V-tolerant CMOS input structures that latch up if stressed beyond absolute-maximum ratings. When interfacing to 3.3 V peripherals, use a level translator (e.g., 74LVTH245) rather than direct connection; do not rely on the input clamp diodes for voltage translation. Do not leave unused I/O pins floating - configure them as outputs driving low or as inputs with internal pull-ups enabled, otherwise floating inputs can draw ICC and cause oscillation. Always use the JTAG ISP (in-system programmability) feature rather than legacy parallel programmers - the JTAG chain allows field updates without removing the device from the board.
Compliance Information
Lead-free finish indicated by 'N' suffix per Altera/Intel product naming convention. RoHS compliance verified by Micro-Semiconductor and distributor listings. Not AEC-Q100 qualified (automotive grade not available for MAX 9000 family). REACH, halogen-free, and conflict-minerals status not explicitly published in available data sources.
