EPM9320LC84-15 vs EPM9320ALC84-10N Comparison
Detailed side-by-side comparison of EPM9320LC84-15 by Intel and EPM9320ALC84-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320LC84-15 | EPM9320ALC84-10N |
|---|---|---|
| Brand | Intel | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Series | EPM9320 | MAX 9000A |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | — |
| Usable Gates | 6,000 | — |
| Logic Array Blocks (LABs) | 20 | — |
| Propagation Delay (tPD) | 15 ns (max) | 10 ns |
| Maximum Clock Frequency | 117.6 MHz | — |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) | 5.0 V nominal |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG | — |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant | — |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) | 84-Pin PLCC (Plastic Leaded Chip Carrier) |
| Mounting Type | Surface Mount | Through-Hole / Socket |
| Operating Temperature | -40C to +85C (commercial) [DATA_NEEDED: exact grade] | — |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) | — |
| Built-in Pull-up Resistors | Yes, on every I/O pin | — |
| Architecture Feature | Pin-locking across design iterations | — |
| RoHS Status | [DATA_NEEDED: confirm from manufacturer] | — |
| Number of Macrocells | — | 320 |
| Number of Gates | — | 6,000 |
| Number of Logic Array Blocks (LABs) | — | 16 |
| User I/O Pins | — | 60 |
| Maximum Internal Frequency (fCNT) | — | 144.9 MHz |
| Operating Temperature Range | — | 0C to +70C (Commercial) |
| Programmable Technology | — | EEPROM (in-system programmable) |
| Programming Interface | — | JTAG (IEEE 1149.1) |
| Part Status | — | Obsolete |