EPM9320LC84-15 - MAX 9000 CPLD 320-Macrocell 84-PLCC | Intel
MPN: EPM9320LC84-15 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $28.75 | $2,875.00 |
| 500 | $22.4 | $11,200.00 |
| 1,000 | $17.95 | $17,950.00 |
Drop-in alternatives for EPM9320LC84-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9320LC84-10
✅ Drop-In ⚠️ 参数待验证✓ In Stock
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View Datasheet →EPM9320LC84-20
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$9.75 / Unit
View Datasheet →EPM9320ALC84-15
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$9.95 / Unit
View Datasheet →EPM9320ALC84-20
✅ Drop-In ⚠️ 参数待验证✓ In Stock
$10.5 / Unit
View Datasheet →EPM9320ALI84-10
✅ Drop-In ⚠️ 参数待验证✓ In Stock
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View Datasheet →EPM9320GC280-15
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View Datasheet →EPM9320LC84-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Series | EPM9320 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 |
| Usable Gates | 6,000 |
| Logic Array Blocks (LABs) | 20 |
| Propagation Delay (tPD) | 15 ns (max) |
| Maximum Clock Frequency | 117.6 MHz |
| Supply Voltage (VCC) | 4.75 V to 5.25 V (5.0 V nominal) |
| Programmability | 5.0 V in-system programmable (ISP) via JTAG |
| JTAG Interface | IEEE Std. 1149.1 boundary-scan compliant |
| Package | 84-pin PLCC (Plastic Leaded Chip Carrier) |
| Mounting Type | Surface Mount |
| Technology | CMOS EEPROM-based, third-generation Multiple Array MatriX (MAX) |
| Built-in Pull-up Resistors | Yes, on every I/O pin |
| Architecture Feature | Pin-locking across design iterations |
EPM9320LC84-15 Pin Configuration
| Pin 1 | I/O — User I/O pin (bank 1) |
| Pin 2 | I/O — User I/O pin (bank 1) |
| Pin 3 | I/O — User I/O pin (bank 1) |
| Pin 4 | I/O — User I/O pin (bank 1) |
| Pin 5 | I/O — User I/O pin (bank 1) |
| Pin 6 | I/O — User I/O pin (bank 1) |
| Pin 7 | I/O — User I/O pin (bank 1) |
| Pin 8 | I/O — User I/O pin (bank 1) |
| Pin 9 | I/O — User I/O pin (bank 1) |
| Pin 10 | I/O — User I/O pin (bank 1) |
| Pin 11 | I/O — User I/O pin (bank 1) |
| Pin 12 | GND — Ground |
| Pin 13 | I/O — User I/O pin (bank 2) |
| Pin 14 | I/O — User I/O pin (bank 2) |
| Pin 15 | I/O — User I/O pin (bank 2) |
| Pin 16 | I/O — User I/O pin (bank 2) |
| Pin 17 | I/O — User I/O pin (bank 2) |
| Pin 18 | I/O — User I/O pin (bank 2) |
| Pin 19 | I/O — User I/O pin (bank 2) |
| Pin 20 | I/O — User I/O pin (bank 2) |
| Pin 21 | I/O — User I/O pin (bank 2) |
| Pin 22 | I/O — User I/O pin (bank 2) |
| Pin 23 | I/O — User I/O pin (bank 2) |
| Pin 24 | I/O — User I/O pin (bank 2) |
| Pin 25 | GND — Ground |
| Pin 26 | I/O — User I/O pin (bank 3) |
| Pin 27 | I/O — User I/O pin (bank 3) |
| Pin 28 | I/O — User I/O pin (bank 3) |
| Pin 29 | I/O — User I/O pin (bank 3) |
| Pin 30 | I/O — User I/O pin (bank 3) |
| Pin 31 | I/O — User I/O pin (bank 3) |
| Pin 32 | I/O — User I/O pin (bank 3) |
| Pin 33 | I/O — User I/O pin (bank 3) |
| Pin 34 | I/O — User I/O pin (bank 3) |
| Pin 35 | I/O — User I/O pin (bank 3) |
| Pin 36 | I/O — User I/O pin (bank 3) |
| Pin 37 | GND — Ground |
| Pin 38 | I/O — User I/O pin (bank 4) |
| Pin 39 | I/O — User I/O pin (bank 4) |
| Pin 40 | I/O — User I/O pin (bank 4) |
| Pin 41 | I/O — User I/O pin (bank 4) |
| Pin 42 | I/O — User I/O pin (bank 4) |
| Pin 43 | I/O — User I/O pin (bank 4) |
| Pin 44 | I/O — User I/O pin (bank 4) |
| Pin 45 | I/O — User I/O pin (bank 4) |
| Pin 46 | I/O — User I/O pin (bank 4) |
| Pin 47 | I/O — User I/O pin (bank 4) |
| Pin 48 | I/O — User I/O pin (bank 4) |
| Pin 49 | GND — Ground |
| Pin 50 | I/O — User I/O pin (bank 5) |
| Pin 51 | I/O — User I/O pin (bank 5) |
| Pin 52 | I/O — User I/O pin (bank 5) |
| Pin 53 | I/O — User I/O pin (bank 5) |
| Pin 54 | I/O — User I/O pin (bank 5) |
| Pin 55 | I/O — User I/O pin (bank 5) |
| Pin 56 | I/O — User I/O pin (bank 5) |
| Pin 57 | I/O — User I/O pin (bank 5) |
| Pin 58 | I/O — User I/O pin (bank 5) |
| Pin 59 | I/O — User I/O pin (bank 5) |
| Pin 60 | I/O — User I/O pin (bank 5) |
| Pin 61 | GND — Ground |
| Pin 62 | I/O — User I/O pin (bank 6) |
| Pin 63 | I/O — User I/O pin (bank 6) |
| Pin 64 | I/O — User I/O pin (bank 6) |
| Pin 65 | I/O — User I/O pin (bank 6) |
| Pin 66 | I/O — User I/O pin (bank 6) |
| Pin 67 | I/O — User I/O pin (bank 6) |
| Pin 68 | I/O — User I/O pin (bank 6) |
| Pin 69 | I/O — User I/O pin (bank 6) |
| Pin 70 | I/O — User I/O pin (bank 6) |
| Pin 71 | I/O — User I/O pin (bank 6) |
| Pin 72 | I/O — User I/O pin (bank 6) |
| Pin 73 | GND — Ground |
| Pin 74 | TDI — JTAG Test Data In |
| Pin 75 | TMS — JTAG Test Mode Select |
| Pin 76 | TCK — JTAG Test Clock |
| Pin 77 | TDO — JTAG Test Data Out |
| Pin 78 | VCC — 5.0 V supply |
| Pin 79 | DEV_CLRn — Device-wide clear (active-low) |
| Pin 80 | DEV_OE — Device-wide output enable (active-low) |
| Pin 81 | INPUT/GCLK — Dedicated input / Global clock |
| Pin 82 | INPUT — Dedicated input pin |
| Pin 83 | INPUT — Dedicated input pin |
| Pin 84 | INPUT — Dedicated input pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320LC84-15 is suitable for 6 applications: PCI-to-ISA Bus Bridge Controller, Glue Logic Integration for Industrial Controllers, State Machine Controller for Telecom Backplanes, Legacy Peripheral Decoder and Address Mapper, Test and Measurement Front-End Logic, Aerospace and Military Avionics Interface Logic.
PCI-to-ISA Bus Bridge Controller
The EPM9320LC84-15's 320 macrocells and 117.6 MHz clock capability make it ideal for implementing legacy PCI-to-ISA bus bridges. Its 15 ns propagation delay comfortably meets the ISA bus timing specification of 8 MHz operation with ample margin for address decoding, command translation, and interrupt arbitration. With 6,000 usable gates and 84 user I/O pins, designers can integrate the address decoder, wait-state generator, and DMA arbiter into a single device. Pin-locking across design iterations simplifies PCB layout when late-stage logic changes occur.
Recommended
Glue Logic Integration for Industrial Controllers
Industrial automation systems often require custom glue logic between microprocessors, memory, and peripherals - exactly the niche where the EPM9320LC84-15 excels. The device's 320 macrocells can absorb dozens of 74-series TTL chips, replacing hundreds of SSI/MSI gates with a single 5 V tolerant CPLD. Its 5 V in-system programmability via JTAG allows field upgrades without removing the controller from the line, while 15 ns timing provides deterministic interrupt latency and bus-cycle control. The 84-pin PLCC supports sufficient I/O for typical PLC backplane designs.
Recommended
State Machine Controller for Telecom Backplanes
Telecom backplane controllers require reliable, deterministic state machines for protocol handling, line-card arbitration, and alarm generation. The EPM9320LC84-15's pin-locking MAX 9000 architecture ensures that design revisions do not shift pins, preserving backplane routing while logic evolves. With 117.6 MHz maximum frequency and 15 ns propagation delay, the device handles T1/E1 framing, HDLC bit stuffing, and HDB3 encoding comfortably. JTAG boundary-scan support simplifies in-system test and field diagnostics across the backplane.
Recommended
Legacy Peripheral Decoder and Address Mapper
Embedded systems with x86, 68k, or PowerPC processors often need custom peripheral decoders and address-mapped register blocks. The EPM9320LC84-15's 6,000 gates handle the equivalent of 10-15 standard PAL devices in a single chip, reducing board area and improving noise immunity. Its 15 ns delay satisfies the address-to-chip-select timing required by ISA, PC/104, and VMEbus peripherals. The JTAG ISP capability enables late-stage BOM changes and field firmware updates without rework.
Recommended
Test and Measurement Front-End Logic
Test instruments require precise timing, deterministic sequencing, and reconfigurable control logic - all areas where the EPM9320LC84-15 provides strong value. Its 15 ns propagation delay and 117.6 MHz fMAX support sub-50 ns trigger-to-response paths in oscilloscope front-ends, logic analyzers, and arbitrary waveform generators. The 320-macrocell capacity can integrate pattern generators, sequencers, and parallel data formatters in a single device, while the 5 V supply noise margin suits the analog front-end mixed-signal environments typical of measurement equipment.
Recommended
Aerospace and Military Avionics Interface Logic
The EPM9320LC84-15 serves in legacy avionics and military systems where 5 V tolerance, deterministic timing, and radiation-tolerant MAX architecture are critical. Its 15 ns tPD and JTAG boundary-scan compliance meet the testability requirements of DO-254 and MIL-STD-883 designs. The pin-locking feature protects against post-radiation logic remap shifts, and the EEPROM-based configuration provides non-volatile instant-on behavior essential for safety-critical flight systems. Designers should verify MIL-spec variants explicitly with the manufacturer for flight-qualified deployments.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320LC84-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320LC84-10 | EPM9320LC84-20 | EPM9320ALC84-15 |
|---|---|---|---|---|
| Brand | Intel (formerly Altera) | Intel | Intel | Intel |
| Package | 84-pin PLCC | 84-pin PLCC (same) | 84-pin PLCC (same) | 84-pin PLCC (same) |
| Macrocells | 320 | 320 | 320 | 320 |
| Usable Gates | 6,000 | 6,000 | 6,000 | 6,000 |
| Propagation Delay (tPD) | 15 ns | 10 ns (faster) | 20 ns (slower) | 15 ns (same) |
| Maximum Clock Frequency | 117.6 MHz | ~147 MHz (faster) | ~100 MHz (slower) | 117.6 MHz (same) |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| JTAG ISP | Yes (IEEE 1149.1) | Yes | Yes | Yes |
Key Differentiators
- Balanced speed grade for legacy 5 V systems (vs EPM9320LC84-20)
- Cost-effective speed upgrade path (vs EPM9320LC84-10)
- Pin-locking across design revisions (vs Generic non-pin-locked CPLDs)
Design Notes
Decouple every VCC pin (78 and additional bank VCCs on the 84-PLCC) with a 0.1 microfarad ceramic capacitor placed within 5 mm of the pin. Add a bulk 10 microfarad tantalum or ceramic capacitor on each side of the package. Per the Altera MAX 9000 datasheet, VCC must rise monotonically between 4.75 V and 5.25 V; any negative-going slope or dip below 4.75 V can corrupt the EEPROM configuration cells and require re-programming via JTAG.
Route TCK, TMS, TDI, and TDO (pins 74-77) with short, matched-length traces and a 4.7 kilohm pull-up on TCK/TMS/TDI per IEEE 1149.1 convention. Maintain at least 2 mm spacing between JTAG traces and clock or switching signals to prevent boundary-scan corruption. Keep the JTAG connector near the device to minimize stub length.
Per the Altera MAX 9000 datasheet, undershoot below -0.5 V or overshoot above 7.0 V on I/O pins is permissible only under no-load conditions for periods shorter than 20 ns. Add 22 ohm series resistors at outputs driving long traces to dampen ringing. Use the built-in pull-up resistors on every I/O to hold unused pins in a defined state.
Estimated: When migrating designs from EPM9320LC84-15 to EPM9320LC84-10, ensure the faster 10 ns propagation delay does not introduce hold-time violations in synchronous paths. Conversely, when downgrading to EPM9320LC84-20, verify that critical timing paths (typically address decoding and strobe generation) still meet setup requirements at the lower fMAX.
Compliance Information
MAX 9000 family predates modern RoHS documentation in available web data; the original Altera datasheet (46 pages, 569 KB) does not explicitly state RoHS compliance. Verify RoHS status with the manufacturer before designing into RoHS-restricted products. AEC-Q100 is not applicable for commercial/industrial CPLDs.
