EPM9320LI84-20 vs EPM9320ALC84-20 Comparison
Detailed side-by-side comparison of EPM9320LI84-20 by Altera and EPM9320ALC84-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320LI84-20 | EPM9320ALC84-20 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Manufacturer | Altera (acquired by Intel) | — |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EPLD (Erasable Programmable Logic Device) |
| Macrocells | 320 | 320 |
| User I/Os | 60 | — |
| Package | 84-PLCC (J-Lead, plastic LCC) | PLCC-84 |
| Propagation Delay (tPD) | 20 ns | — |
| Internal Frequency | 118 MHz | — |
| Supply Voltage | 5.0 V | 5.0 V |
| Logic Family | CMOS, EEPROM-based | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | — |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) | — |
| Operating Temperature | -40 C to +85 C (industrial) | [DATA_NEEDED: commercial or industrial grade] |
| Mounting Type | Surface Mount (PLCC socket-compatible) | Surface Mount (PLCC socket compatible) |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: per Altera datasheet] |
| Process Technology | High-performance CMOS EEPROM | 0.5 µm CMOS EEPROM |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/Os | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 20 ns |
| Programmability | — | In-system via IEEE 1149.1 JTAG |
| Configuration Memory | — | Non-volatile EEPROM |
| Boundary Scan | — | JTAG IEEE 1149.1 |
| Design Software | — | MAX+PLUS II / Quartus II (legacy) |