EPM9320LI84-20 - MAX 9000 CPLD, 320 Macro, 60 I/O | Altera
MPN: EPM9320LI84-20 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $24.75 | $247.50 |
| 100 | $19.9 | $1,990.00 |
| 500 | $15.4 | $7,700.00 |
| 1,000 | $12.8 | $12,800.00 |
Drop-in alternatives for EPM9320LI84-20 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9320LC84-15
β Drop-Inβ In Stock
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View Datasheet βEPM9320LC84-10
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View Datasheet βEPM9320LC84-20
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$9.75 / Unit
View Datasheet βEPM9320LC84-20N
β Drop-Inβ In Stock
$10.25 / Unit
View Datasheet βEPM9320ALC84-10
β Drop-Inβ In Stock
$19.8 / Unit
View Datasheet βEPM9320ALI84-10
β Drop-Inβ In Stock
$19.95 / Unit
View Datasheet βEPM9320LI84-20 Maximum Ratings & Electrical Characteristics
| Manufacturer | Altera (acquired by Intel) |
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 |
| User I/Os | 60 |
| Package | 84-PLCC (J-Lead, plastic LCC) |
| Propagation Delay (tPD) | 20 ns |
| Internal Frequency | 118 MHz |
| Supply Voltage | 5.0 V |
| Logic Family | CMOS, EEPROM-based |
| Architecture | Multiple Array MatriX (MAX) - third generation |
| In-System Programmability | Yes (IEEE 1149.1 JTAG) |
| Operating Temperature | -40 C to +85 C (industrial) |
| Mounting Type | Surface Mount (PLCC socket-compatible) |
| Process Technology | High-performance CMOS EEPROM |
EPM9320LI84-20 Pin Configuration
| Pin 1 | I/O β User I/O - bank A |
| Pin 2 | I/O β User I/O - bank A |
| Pin 3 | I/O β User I/O - bank A |
| Pin 4 | I/O β User I/O - bank A |
| Pin 5 | I/O β User I/O - bank A |
| Pin 6 | I/O β User I/O - bank A |
| Pin 7 | I/O β User I/O - bank A |
| Pin 8 | I/O β User I/O - bank A |
| Pin 9 | I/O β User I/O - bank A |
| Pin 10 | I/O β User I/O - bank A |
| Pin 11 | GND β Ground |
| Pin 12 | I/O β User I/O - bank B |
| Pin 13 | I/O β User I/O - bank B |
| Pin 14 | I/O β User I/O - bank B |
| Pin 15 | I/O β User I/O - bank B |
| Pin 16 | I/O β User I/O - bank B |
| Pin 17 | I/O β User I/O - bank B |
| Pin 18 | I/O β User I/O - bank B |
| Pin 19 | I/O β User I/O - bank B |
| Pin 20 | I/O β User I/O - bank B |
| Pin 21 | I/O β User I/O - bank B |
| Pin 22 | I/O β User I/O - bank B |
| Pin 23 | I/O β User I/O - bank B |
| Pin 24 | I/O β User I/O - bank B |
| Pin 25 | VCC β 5.0 V supply |
| Pin 26 | I/O β User I/O - bank C |
| Pin 27 | I/O β User I/O - bank C |
| Pin 28 | I/O β User I/O - bank C |
| Pin 29 | I/O β User I/O - bank C |
| Pin 30 | I/O β User I/O - bank C |
| Pin 31 | I/O β User I/O - bank C |
| Pin 32 | I/O β User I/O - bank C |
| Pin 33 | I/O β User I/O - bank C |
| Pin 34 | I/O β User I/O - bank C |
| Pin 35 | I/O β User I/O - bank C |
| Pin 36 | I/O β User I/O - bank C |
| Pin 37 | I/O β User I/O - bank C |
| Pin 38 | I/O β User I/O - bank C |
| Pin 39 | GND β Ground |
| Pin 40 | I/O β User I/O - bank D |
| Pin 41 | I/O β User I/O - bank D |
| Pin 42 | I/O β User I/O - bank D |
| Pin 43 | I/O β User I/O - bank D |
| Pin 44 | I/O β User I/O - bank D |
| Pin 45 | TDI β JTAG Test Data In |
| Pin 46 | I/O β User I/O - bank D |
| Pin 47 | I/O β User I/O - bank D |
| Pin 48 | I/O β User I/O - bank D |
| Pin 49 | I/O β User I/O - bank D |
| Pin 50 | I/O β User I/O - bank D |
| Pin 51 | I/O β User I/O - bank D |
| Pin 52 | I/O β User I/O - bank D |
| Pin 53 | I/O β User I/O - bank D |
| Pin 54 | GND β Ground |
| Pin 55 | I/O β User I/O - bank D |
| Pin 56 | I/O β User I/O - bank D |
| Pin 57 | TMS β JTAG Test Mode Select |
| Pin 58 | I/O β User I/O - bank D |
| Pin 59 | TCK β JTAG Test Clock |
| Pin 60 | I/O β User I/O - bank D |
| Pin 61 | I/O β User I/O - bank D |
| Pin 62 | VCC β 5.0 V supply |
| Pin 63 | I/O β User I/O - bank A |
| Pin 64 | I/O β User I/O - bank A |
| Pin 65 | I/O β User I/O - bank A |
| Pin 66 | I/O β User I/O - bank A |
| Pin 67 | I/O β User I/O - bank A |
| Pin 68 | I/O β User I/O - bank A |
| Pin 69 | I/O β User I/O - bank A |
| Pin 70 | I/O β User I/O - bank A |
| Pin 71 | I/O β User I/O - bank A |
| Pin 72 | I/O β User I/O - bank A |
| Pin 73 | I/O β User I/O - bank A |
| Pin 74 | GND β Ground |
| Pin 75 | I/O β User I/O - bank B |
| Pin 76 | I/O β User I/O - bank B |
| Pin 77 | I/O β User I/O - bank B |
| Pin 78 | I/O β User I/O - bank B |
| Pin 79 | I/O β User I/O - bank B |
| Pin 80 | I/O β User I/O - bank B |
| Pin 81 | I/O β User I/O - bank B |
| Pin 82 | I/O β User I/O - bank B |
| Pin 83 | TDO β JTAG Test Data Out |
| Pin 84 | I/O β User I/O - bank B |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320LI84-20 is suitable for 6 applications: High-Density Address Decoding for 32/64-bit Microprocessor Systems, Peripheral Bus Interface Bridge (PCI/ISA/VME), Industrial Automation State-Machine Controller, JTAG-Based In-System Configuration Controller for Downstream Devices, Legacy Multi-PAL Glue-Logic Consolidation, Telecommunications Backplane Glue Logic.
High-Density Address Decoding for 32/64-bit Microprocessor Systems
The EPM9320LI84-20's 320-macrocell capacity and 60 user I/Os make it well-suited to consolidate address decoding, chip-select generation, and wait-state insertion for 32-bit and 64-bit microprocessor/memory systems. A single device can replace ten or more discrete 22V10/32-macrocell PALs, shrinking board area and reducing BOM count. With 20 ns tPD, the part reliably decodes 50 MHz memory buses; engineers targeting higher speeds should select the -15 or -10 speed grade. The 84-PLCC package's high I/O count accommodates wide address buses (A0-A31) plus dedicated chip-select outputs without external steering logic. JTAG ISP enables post-layout logic changes without removing the part.
Recommended
Peripheral Bus Interface Bridge (PCI/ISA/VME)
In legacy peripheral bus systems the EPM9320LI84-20 acts as a glue-logic bridge, generating control signals, managing bus arbitration, and providing timing-edge alignment between asynchronous peripherals. The 60 user I/Os comfortably accommodate full 32-bit data plus 32-bit address plus control (REQ#, GNT#, FRAME#, IRDY#) signals. The 5.0 V tolerant I/O matches PCI/ISA/VME logic levels directly without external transceivers. Non-volatile EEPROM configuration means the bridge comes up in a defined state without external boot PROMs. Industrial temperature rating supports telecom and industrial backplane applications. Pair with a supervisory reset device and bus transceivers for a complete bridge solution.
Recommended
Industrial Automation State-Machine Controller
The EPM9320LI84-20 is well-suited to industrial state-machine controllers, where deterministic timing (CPLDs guarantee fixed 20 ns tPD regardless of logic utilization) is more important than raw gate count. Its 320 macrocells accommodate complex multi-state sequencers for PLC I/O modules, motor-control front-ends, and safety interlock logic. The industrial -40 C to +85 C temperature range supports factory-floor deployment. EEPROM non-volatility ensures the controller enters a known safe state at every power-up, critical for safety applications. The 84-PLCC package is socket-compatible for field replacement. JTAG ISP allows on-line firmware updates during commissioning without depaneling.
Recommended
JTAG-Based In-System Configuration Controller for Downstream Devices
The EPM9320LI84-20 can serve as a master JTAG controller, sequencing configuration bitstreams to multiple downstream FPGAs, CPLDs, and boundary-scan devices. Its 320 macrocells implement the TAP controller state machine plus per-device instruction register management, while 60 I/Os drive TDI/TDO daisy-chains across multiple target devices. Non-volatile EEPROM configuration means the CPLD comes up as the JTAG master without an external processor. Industrial temperature grade supports outdoor and factory-floor installations. With 20 ns tPD, the part comfortably drives JTAG chains at the standard TCK rates. JTAG ISP for the CPLD itself uses the same chain.
Recommended
Legacy Multi-PAL Glue-Logic Consolidation
Board designers often need to replace aging 22V10, 26V12, or 32-macrocell PALs whose silicon is end-of-life; the EPM9320LI84-20 provides 10x the logic density in a single 84-PLCC socket, directly replacing ten PALs. The non-volatile EEPROM means the consolidated design boots without an external PROM. JTAG ISP enables incremental port-by-port migration from discrete PALs: each migration step reprograms the CPLD with one additional PAL's logic, verified against the original part before removing it. Industrial temperature rating and PLCC packaging suit legacy systems whose sockets cannot accommodate leadless QFN/BGA packages.
Recommended
Telecommunications Backplane Glue Logic
In telecom backplane applications the EPM9320LI84-20 provides high-density, deterministic glue logic for line-card interface controllers, where it manages HDB3/AMI encoding, clock-data recovery synchronization, and alarm-status multiplexing. The 5 V I/O directly interfaces with legacy telecom ASICs without level shifting, and the 60 user I/Os accommodate multi-port serial links plus parallel control/status buses. Industrial temperature rating and high reliability of EEPROM-based configuration suit carrier-grade equipment. The 84-PLCC package and through-hole-compatible socket mounting suit legacy backplane form factors that cannot accept fine-pitch SMT. JTAG ISP simplifies field firmware updates across geographically dispersed installations.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320LI84-20 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320LC84-15 | EPM9320LC84-10 | EPM9320LC84-20 | EPM9320LC84-20N | EPM9320ALC84-10 | EPM9320ALI84-10 |
|---|---|---|---|---|---|---|---|
| Package | 84-PLCC (J-Lead) | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same | 84-PLCC (J-Lead) - same |
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Propagation Delay (tPD) | 20 ns | 15 ns | 10 ns | 20 ns | 20 ns | 10 ns | 10 ns |
| Macrocells | 320 | 320 | 320 | 320 | 320 | 320 | 320 |
| User I/Os | 60 | 60 | 60 | 60 | 60 | 60 | 60 |
| Operating Temperature | -40 C to +85 C (industrial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | 0 C to +70 C (commercial) | -40 C to +85 C (extended) | -40 C to +85 C (industrial) |
| Internal Frequency (max) | 118 MHz | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
| Architecture | MAX 9000 (3rd gen) | MAX 9000 (3rd gen) | MAX 9000 (3rd gen) | MAX 9000 (3rd gen) | MAX 9000 (3rd gen) | MAX 9000 (3rd gen) | MAX 9000 (3rd gen) |
| In-System Programmability | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Lifecycle Status | Obsolete / LTB | Obsolete / LTB | Obsolete / LTB | Obsolete / LTB | Obsolete / LTB | Obsolete / LTB | Obsolete / LTB |
Key Differentiators
- Industrial temperature grade in the -20 speed pinout (vs EPM9320LC84-20)
- Highest-density 84-PLCC MAX 9000 device with ISP (vs EPM7160SLC84-10)
- Direct cross-generation drop-in compatibility (vs EPM9320LC84-15)
Design Notes
The 84-PLCC J-lead package has a 1.27 mm pitch and is most commonly used in through-hole sockets; for surface-mount reflow, profile the package to JEDEC J-STD-020 MSL-3 conditions with a peak body temperature of 245 C and 60 s above 183 C. PLCC sockets from 3M, AMP, and Yamaichi accept this device and simplify field replacement; however, the socket adds ~6 pF per pin which may impact high-speed signal edges above 50 MHz. Reserve a JTAG header on every board that uses this device, even in production: the 5-pin header (TCK/TMS/TDI/TDO/GND) enables in-field firmware updates without depaneling.
Although the MAX 9000 architecture guarantees fixed 20 ns tPD regardless of routing, the I/O buffers do not have slew-rate control. For signals crossing PLCC socket inductance (estimated 6-10 nH per pin), add 33 ohm series damping resistors near the CPLD outputs when driving buses longer than 50 mm or above 25 MHz. Decouple each VCC pin (pins 25 and 62) with a 100 nF X7R ceramic plus a 10 uF tantalum bulk capacitor placed within 5 mm of the pin. Multiple GND pins (11, 39, 54, 74) should each have a dedicated via to the ground plane; do not share GND returns with high-current switching circuits.
Three pitfalls to avoid when designing with the EPM9320LI84-20. First, do not assume speed-grade compatibility across the family: substituting a -10 (10 ns) device into a board designed for the -20 (20 ns) without re-running timing simulation may produce hold-time violations in fast paths; always re-fit the design for the actual speed grade. Second, the MAX 9000 ISP programming algorithm requires VCC within 4.75-5.25 V during JTAG operations; out-of-spec voltage causes programming failures that may appear as silent bit-cell corruption. Third, when using the device as a JTAG master for downstream devices, ensure the CPLD is first in the JTAG chain (TDI input) so it can sequence the chain without contention; misordered chains cause BYPASS register corruption.
Compliance Information
RoHS/REACH status not stated in distributor pages. The EPM9320LI84-20N suffix variant denotes lead-free / Pb-free reflow-rated assembly; base EPM9320LI84-20 was originally released in SnPb finish. Contact Intel/Altera legacy support for formal RoHS/REACH documentation. AEC-Q100 not applicable - this is a commercial/industrial programmable logic device, not an automotive-grade IC.
