EPM9320RC208-15N vs EPM9320RC208-20 Comparison
Detailed side-by-side comparison of EPM9320RC208-15N by Intel and EPM9320RC208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320RC208-15N | EPM9320RC208-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Nrnd | Obsolete |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $21.90 |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 6,000 | 6,000 |
| Macro Cells | 320 | β |
| Flip-Flops | 484 | β |
| Configurable I/O Lines | 128 | β |
| Propagation Delay (tPD) | 15 ns | β |
| Maximum Clock Frequency | 117.6 MHz | β |
| Supply Voltage | 5.0 V | β |
| I/O Voltage Compatibility | 3.3 V or 5 V | β |
| Configuration Technology | CMOS EEPROM (non-volatile) | β |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | β |
| Package | 208-pin RQFP (PowerQuad Flat Pack) | 208-RQFP, exposed pad (208-BFQFP) |
| Terminal Pitch | 0.5 mm | β |
| Operating Temperature Range | 0C to +70C (commercial) | β |
| Mounting Type | Surface Mount | Surface Mount |
| Packaging | Tray | β |
| RoHS Status | [DATA_NEEDED: RoHS status] | β |
| Macrocells | β | 320 |
| Logic Array Blocks (LABs) | β | 20 |
| Maximum I/O Pins | β | 132 |
| Propagation Delay (tPD max) | β | 20 ns |
| Supply Voltage (VCCINT) | β | 4.75 V to 5.25 V |
| Programming Technology | β | EEPROM, in-system programmable (ISP) |
| Boundary-Scan Interface | β | IEEE Std. 1149.1 (JTAG) |
| Operating Temperature | β | 0 Β°C to 70 Β°C (commercial) |
| Architecture | β | Multiple Array Matrix (MAX), 3rd generation |
| Process Technology | β | CMOS, 5.0 V EEPROM |
| Reprogrammability | β | Yes, unlimited ISP cycles |