EPM9320RC208-20 - 320-Macrocell MAX 9000 CPLD, 20ns | Altera
MPN: EPM9320RC208-20 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $38.5 | $38.50 |
| 10 | $34.2 | $342.00 |
| 100 | $29.8 | $2,980.00 |
| 500 | $25.4 | $12,700.00 |
| 1,000 | $21.9 | $21,900.00 |
Drop-in alternatives for EPM9320RC208-20 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet →EPM9320RC208-20 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 |
| Logic Array Blocks (LABs) | 20 |
| Usable Gates | 6,000 |
| Maximum I/O Pins | 132 |
| Propagation Delay (tPD max) | 20 ns |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V |
| Programming Technology | EEPROM, in-system programmable (ISP) |
| Boundary-Scan Interface | IEEE Std. 1149.1 (JTAG) |
| Operating Temperature | 0 °C to 70 °C (commercial) |
| Package | 208-RQFP, exposed pad (208-BFQFP) |
| Mounting Type | Surface Mount |
| Architecture | Multiple Array Matrix (MAX), 3rd generation |
| Process Technology | CMOS, 5.0 V EEPROM |
| Reprogrammability | Yes, unlimited ISP cycles |
EPM9320RC208-20 Pin Configuration
| Pin 1 | I/O — User I/O pin (pin 1 of 208-RQFP) |
| Pin 2 | I/O — User I/O pin |
| Pin 3 | I/O — User I/O pin |
| Pin 4 | I/O — User I/O pin |
| Pin 5 | I/O — User I/O pin |
| Pin 6 | GND — Ground |
| Pin 7 | I/O — User I/O pin |
| Pin 8 | I/O — User I/O pin |
| Pin 9 | I/O — User I/O pin |
| Pin 10 | I/O — User I/O pin |
| Pin 11 | I/O — User I/O pin |
| Pin 12 | VCC — 5.0 V supply (VCCINT) |
| Pin 13 | I/O — User I/O pin |
| Pin 14 | I/O — User I/O pin |
| Pin 15 | I/O — User I/O pin |
| Pin 16 | I/O — User I/O pin |
| Pin 17 | I/O — User I/O pin |
| Pin 18 | I/O — User I/O pin |
| Pin 19 | GND — Ground |
| Pin 20 | I/O — User I/O pin |
| Pin 21 | I/O — User I/O pin |
| Pin 22 | I/O — User I/O pin |
| Pin 23 | I/O — User I/O pin |
| Pin 24 | I/O — User I/O pin |
| Pin 25 | TDI — JTAG Test Data In (IEEE 1149.1) |
| Pin 26 | TMS — JTAG Test Mode Select |
| Pin 27 | TCK — JTAG Test Clock |
| Pin 28 | VCC — 5.0 V supply |
| Pin 29 | I/O — User I/O pin |
| Pin 30 | I/O — User I/O pin |
| Pin 31 | I/O — User I/O pin |
| Pin 32 | I/O — User I/O pin |
| Pin 33 | I/O — User I/O pin |
| Pin 34 | GND — Ground |
| Pin 35 | I/O — User I/O pin |
| Pin 36 | I/O — User I/O pin |
| Pin 37 | I/O — User I/O pin |
| Pin 38 | I/O — User I/O pin |
| Pin 39 | I/O — User I/O pin |
| Pin 40 | I/O — User I/O pin |
| Pin 41 | I/O — User I/O pin |
| Pin 42 | VCC — 5.0 V supply |
| Pin 43 | I/O — User I/O pin |
| Pin 44 | I/O — User I/O pin |
| Pin 45 | I/O — User I/O pin |
| Pin 46 | I/O — User I/O pin |
| Pin 47 | I/O — User I/O pin |
| Pin 48 | I/O — User I/O pin |
| Pin 49 | GND — Ground |
| Pin 50 | I/O — User I/O pin |
| Pin 51 | I/O — User I/O pin |
| Pin 52 | I/O — User I/O pin |
| Pin 53 | I/O — User I/O pin |
| Pin 54 | I/O — User I/O pin |
| Pin 55 | I/O — User I/O pin |
| Pin 56 | I/O — User I/O pin |
| Pin 57 | VCC — 5.0 V supply |
| Pin 58 | I/O — User I/O pin |
| Pin 59 | I/O — User I/O pin |
| Pin 60 | I/O — User I/O pin |
| Pin 61 | I/O — User I/O pin |
| Pin 62 | I/O — User I/O pin |
| Pin 63 | I/O — User I/O pin |
| Pin 64 | GND — Ground |
| Pin 65 | I/O — User I/O pin |
| Pin 66 | I/O — User I/O pin |
| Pin 67 | I/O — User I/O pin |
| Pin 68 | I/O — User I/O pin |
| Pin 69 | I/O — User I/O pin |
| Pin 70 | I/O — User I/O pin |
| Pin 71 | I/O — User I/O pin |
| Pin 72 | VCC — 5.0 V supply |
| Pin 73 | I/O — User I/O pin |
| Pin 74 | I/O — User I/O pin |
| Pin 75 | I/O — User I/O pin |
| Pin 76 | I/O — User I/O pin |
| Pin 77 | I/O — User I/O pin |
| Pin 78 | I/O — User I/O pin |
| Pin 79 | GND — Ground |
| Pin 80 | I/O — User I/O pin |
| Pin 81 | I/O — User I/O pin |
| Pin 82 | I/O — User I/O pin |
| Pin 83 | I/O — User I/O pin |
| Pin 84 | I/O — User I/O pin |
| Pin 85 | I/O — User I/O pin |
| Pin 86 | I/O — User I/O pin |
| Pin 87 | VCC — 5.0 V supply |
| Pin 88 | I/O — User I/O pin |
| Pin 89 | I/O — User I/O pin |
| Pin 90 | I/O — User I/O pin |
| Pin 91 | I/O — User I/O pin |
| Pin 92 | I/O — User I/O pin |
| Pin 93 | I/O — User I/O pin |
| Pin 94 | GND — Ground |
| Pin 95 | I/O — User I/O pin |
| Pin 96 | I/O — User I/O pin |
| Pin 97 | I/O — User I/O pin |
| Pin 98 | I/O — User I/O pin |
| Pin 99 | I/O — User I/O pin |
| Pin 100 | I/O — User I/O pin |
| Pin 101 | I/O — User I/O pin |
| Pin 102 | VCC — 5.0 V supply |
| Pin 103 | I/O — User I/O pin |
| Pin 104 | I/O — User I/O pin |
| Pin 105 | I/O — User I/O pin |
| Pin 106 | I/O — User I/O pin |
| Pin 107 | I/O — User I/O pin |
| Pin 108 | I/O — User I/O pin |
| Pin 109 | GND — Ground |
| Pin 110 | I/O — User I/O pin |
| Pin 111 | I/O — User I/O pin |
| Pin 112 | I/O — User I/O pin |
| Pin 113 | I/O — User I/O pin |
| Pin 114 | I/O — User I/O pin |
| Pin 115 | I/O — User I/O pin |
| Pin 116 | I/O — User I/O pin |
| Pin 117 | VCC — 5.0 V supply |
| Pin 118 | I/O — User I/O pin |
| Pin 119 | I/O — User I/O pin |
| Pin 120 | I/O — User I/O pin |
| Pin 121 | I/O — User I/O pin |
| Pin 122 | I/O — User I/O pin |
| Pin 123 | I/O — User I/O pin |
| Pin 124 | GND — Ground |
| Pin 125 | I/O — User I/O pin |
| Pin 126 | I/O — User I/O pin |
| Pin 127 | I/O — User I/O pin |
| Pin 128 | I/O — User I/O pin |
| Pin 129 | I/O — User I/O pin |
| Pin 130 | I/O — User I/O pin |
| Pin 131 | I/O — User I/O pin |
| Pin 132 | VCC — 5.0 V supply |
| Pin 133 | I/O — User I/O pin |
| Pin 134 | I/O — User I/O pin |
| Pin 135 | I/O — User I/O pin |
| Pin 136 | I/O — User I/O pin |
| Pin 137 | I/O — User I/O pin |
| Pin 138 | I/O — User I/O pin |
| Pin 139 | GND — Ground |
| Pin 140 | I/O — User I/O pin |
| Pin 141 | I/O — User I/O pin |
| Pin 142 | I/O — User I/O pin |
| Pin 143 | I/O — User I/O pin |
| Pin 144 | I/O — User I/O pin |
| Pin 145 | I/O — User I/O pin |
| Pin 146 | I/O — User I/O pin |
| Pin 147 | VCC — 5.0 V supply |
| Pin 148 | I/O — User I/O pin |
| Pin 149 | I/O — User I/O pin |
| Pin 150 | I/O — User I/O pin |
| Pin 151 | I/O — User I/O pin |
| Pin 152 | I/O — User I/O pin |
| Pin 153 | I/O — User I/O pin |
| Pin 154 | GND — Ground |
| Pin 155 | I/O — User I/O pin |
| Pin 156 | I/O — User I/O pin |
| Pin 157 | I/O — User I/O pin |
| Pin 158 | I/O — User I/O pin |
| Pin 159 | I/O — User I/O pin |
| Pin 160 | I/O — User I/O pin |
| Pin 161 | I/O — User I/O pin |
| Pin 162 | VCC — 5.0 V supply |
| Pin 163 | I/O — User I/O pin |
| Pin 164 | I/O — User I/O pin |
| Pin 165 | I/O — User I/O pin |
| Pin 166 | I/O — User I/O pin |
| Pin 167 | I/O — User I/O pin |
| Pin 168 | I/O — User I/O pin |
| Pin 169 | GND — Ground |
| Pin 170 | I/O — User I/O pin |
| Pin 171 | I/O — User I/O pin |
| Pin 172 | I/O — User I/O pin |
| Pin 173 | I/O — User I/O pin |
| Pin 174 | I/O — User I/O pin |
| Pin 175 | I/O — User I/O pin |
| Pin 176 | I/O — User I/O pin |
| Pin 177 | VCC — 5.0 V supply |
| Pin 178 | I/O — User I/O pin |
| Pin 179 | I/O — User I/O pin |
| Pin 180 | I/O — User I/O pin |
| Pin 181 | I/O — User I/O pin |
| Pin 182 | I/O — User I/O pin |
| Pin 183 | TDO — JTAG Test Data Out |
| Pin 184 | I/O — User I/O pin |
| Pin 185 | I/O — User I/O pin |
| Pin 186 | I/O — User I/O pin |
| Pin 187 | I/O — User I/O pin |
| Pin 188 | I/O — User I/O pin |
| Pin 189 | I/O — User I/O pin |
| Pin 190 | I/O — User I/O pin |
| Pin 191 | GND — Ground |
| Pin 192 | I/O — User I/O pin |
| Pin 193 | I/O — User I/O pin |
| Pin 194 | I/O — User I/O pin |
| Pin 195 | I/O — User I/O pin |
| Pin 196 | I/O — User I/O pin |
| Pin 197 | I/O — User I/O pin |
| Pin 198 | I/O — User I/O pin |
| Pin 199 | I/O — User I/O pin |
| Pin 200 | I/O — User I/O pin |
| Pin 201 | I/O — User I/O pin |
| Pin 202 | I/O — User I/O pin |
| Pin 203 | I/O — User I/O pin |
| Pin 204 | I/O — User I/O pin |
| Pin 205 | I/O — User I/O pin |
| Pin 206 | I/O — User I/O pin |
| Pin 207 | I/O — User I/O pin |
| Pin 208 | I/O — User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320RC208-20 is suitable for 6 applications: 5 V Industrial Glue-Logic Consolidation, Legacy Microprocessor Address Decoding, Telecom Backplane Bus Interface Bridging, State-Machine Replacement in Test & Measurement, Peripheral Control Logic in Networking Equipment, Safety-Critical Power-On Control Logic.
5 V Industrial Glue-Logic Consolidation
The EPM9320RC208-20's 320 macrocells, 132 user I/O pins, and 5.0 V single-supply operation make it ideal for replacing 8 to 15 discrete 22V10 / GAL / PAL devices with a single instant-on non-volatile CPLD in 5 V industrial controllers. Its deterministic 20 ns tPD across all macrocell paths eliminates the timing-variation issues that plague SRAM-based FPGAs in asynchronous designs, and the IEEE 1149.1 JTAG interface allows board-level boundary-scan test of every I/O pin. Engineers place it between a 5 V microcontroller and legacy peripherals (parallel ADCs, LCD drivers, opto-isolated outputs) to consolidate address decoding, chip-select generation, and timing-strobe logic. The exposed-pad 208-RQFP package dissipates enough heat for the device's typical 1.5 W active power in a sealed industrial enclosure without an external heatsink.
Recommended
Legacy Microprocessor Address Decoding
In 5 V Intel 8086 / 68000 / VME-bus designs the EPM9320RC208-20 replaces dozens of 74LS138 / 74LS139 decoder trees with a single programmable decoder that can map the full 1 MB (or 16 MB) address space into dozens of chip-select regions. Its 132 I/O pins handle wide address-and-control buses directly, and the 20 ns tPD provides two-level decode within a single 8 MHz bus cycle without wait-state insertion. The instant-on EEPROM configuration means decoded chip-selects are valid at the first rising edge of the system clock after power-up - critical for legacy CPUs that fetch the reset vector before any software runs. JTAG boundary-scan verifies every decoded output during manufacturing test, eliminating bed-of-nails fixtures.
Recommended
Telecom Backplane Bus Interface Bridging
The EPM9320RC208-20's 132 I/O pins and 5 V tolerance allow it to bridge between legacy TTL buses (e.g., H.110 CT-bus, SCSA, parallel TDM) and modern FPGAs in telecom line cards. It performs level conditioning, parity generation/checking, and protocol conversion at the backplane edge, isolating the higher-density downstream FPGA from bus contention. The 20 ns tPD is sufficient for 50 MHz backplane operation when used as a pipeline-stage register, and the IEEE 1149.1 JTAG chain integrates seamlessly with the board's existing boundary-scan test infrastructure. Non-volatile EEPROM configuration means the bridge comes up correctly even after a brownout or hot-swap event, which is essential for NEBS-compliant telecom equipment.
Recommended
State-Machine Replacement in Test & Measurement
Test-and-measurement instruments use the EPM9320RC208-20 to implement complex sequencing state machines - scan-chain controllers, multiplexer switching matrices, calibration sequencers - that would otherwise consume dozens of 74LS / 74HC flip-flops. Its 320 macrocells encode multi-state machines with 8 to 10 bits of state plus dozens of transition outputs, all running at deterministic 20 ns latency that keeps stimulus timing reproducible. The 132 I/O pins drive front-panel relays, ADC mux gates, and status LEDs directly without buffer logic. Because the design is stored in on-chip EEPROM, instruments boot into the correct test sequence even in factory-floor environments where power is cycled frequently.
Recommended
Peripheral Control Logic in Networking Equipment
Routers, switches, and media gateways use the EPM9320RC208-20 to consolidate PHY interface glue logic - MDIO bus multiplexing, LED status driving, SFP module presence detect, and packet-classifier pre-processing. Its 5 V I/O compatibility matches the levels used by many legacy PHYs, and the 20 ns propagation delay easily handles the 25 MHz MDC clock. The 320 macrocells encode enough state to drive 24+ SFP cage presence/LED signals plus interrupt-aggregation logic in a single chip. JTAG boundary-scan over all 132 I/Os accelerates board bring-up by detecting solder bridges and open pins during in-circuit test, which is critical when each line card carries dozens of high-density connectors.
Recommended
Safety-Critical Power-On Control Logic
The EPM9320RC208-20's instant-on non-volatile EEPROM behavior makes it ideal for power-on sequencing and watchdog logic in safety-critical systems (medical devices, industrial PLCs, railway signaling). Unlike SRAM FPGAs that require milliseconds of configuration time, this CPLD drives valid outputs within nanoseconds of VCC crossing 4.75 V, ensuring that reset vectors, watchdog strobes, and power-rail enables are present before any downstream host CPU or DSP boots. Its 320 macrocells encode dozens of independent sequencer channels, and the 132 I/O pins drive housekeeping signals directly. The deterministic 20 ns tPD simplifies worst-case timing analysis required by IEC 61508 SIL-2/3 functional-safety documentation.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320RC208-20 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320RC208-15 | EPM9320RC208-15N | EPM9320RC208-10 | EPM9320ARC208-10 |
|---|---|---|---|---|---|
| Brand | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) | Altera (Intel) |
| Package | 208-RQFP (exposed pad) | 208-RQFP (exposed pad) - same | 208-RQFP (exposed pad) - same | 208-RQFP (exposed pad) - same | 208-RQFP (exposed pad) - same |
| Macrocells | 320 | 320 | 320 | 320 | 320 |
| Max I/O | 132 | 132 | 132 | 132 | 132 |
| Propagation Delay (tPD max) | 20 ns | 15 ns (faster) | 15 ns (faster) | 10 ns (faster) | 10 ns (faster) |
| Supply Voltage | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V | 4.75 V to 5.25 V |
| Programming Technology | EEPROM (ISP via JTAG) | EEPROM (ISP via JTAG) | EEPROM (ISP via JTAG) | EEPROM (ISP via JTAG) | EEPROM (ISP via JTAG) |
| Operating Temperature | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C | 0 °C to 70 °C |
| Lifecycle Status | Obsolete | Obsolete (same family) | Obsolete (same family) | Obsolete (same family) | Obsolete (same family) |
Key Differentiators
- Slowest speed grade in the EPM9320RC208 family, lowest secondary-market cost (vs EPM9320RC208-15)
- 320-macrocell density vs lower-end MAX 7000S family members (vs EPM7256SQC208-10)
- MAX 9000 EEPROM instant-on vs MAX II SRAM configuration delay (vs EPM240T100C5N (MAX II))
Design Notes
Solder the exposed thermal pad on the underside of the 208-RQFP package to a PCB ground plane with at least 1 square inch (645 mm²) of copper area. The MAX 9000 device dissipates roughly 1.5 W at 100% macrocell utilization at 5 V, and without the thermal pad soldered junction temperature can exceed 100 °C even at room ambient. Estimate: at 1.5 W with 1 sq-in. copper pour, θJA ≈ 18 °C/W yields a 27 °C rise above 25 °C ambient (52 °C junction), well within the 70 °C commercial ceiling. For sealed industrial enclosures above 50 °C ambient, expand the copper area to 2-3 sq-in. or add forced-air cooling.
Decouple every VCC pin with a 0.1 µF ceramic capacitor placed within 3 mm (0.12 in.) of the supply pin and tie the GND return directly to the inner ground plane via a short via. Add one bulk 10 µF tantalum or aluminum-polymer capacitor near the corner of the package to handle simultaneous-switching-output (SSO) current transients from the 132 I/O pins. Place the JTAG TCK trace away from the I/O banks and add a 10 kΩ pull-up on TMS and TDI, plus a 10 kΩ pull-down on TRST to keep the boundary-scan state machine in known state during power-up.
Do not exceed 5.25 V on VCCINT even momentarily - the EEPROM programming circuits can latch-up above 6 V. Do not leave unused I/O pins floating; configure them in MAX+PLUS II / Quartus as outputs driving '0' or as inputs with internal pull-ups enabled, otherwise floating inputs draw 10-100 µA each and increase total quiescent current. Verify JTAG chain order in BSDL files when multiple MAX devices share one TCK/TMS bus - a reversed chain will pass boundary-scan tests but fail ISP programming. Finally, allow at least 50 ms after VCC stabilizes before initiating JTAG operations because the EEPROM charge pump requires settling time.
Compliance Information
EPM9320RC208-20 predates widespread RoHS conversion requirements; compliance depends on the specific date code and assembly variant. Standard Altera lead-finish parts carry SnPb solder, while lead-free variants (suffix 'N' such as EPM9320RC208-15N) are RoHS-compliant. Request specific compliance certificates from the supplier for each lot. Not AEC-Q100 qualified (industrial/consumer grade only).
