EPM9320RC208-20 vs EPM9320RC208-10 Comparison
Detailed side-by-side comparison of EPM9320RC208-20 by Altera and EPM9320RC208-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9320RC208-20 | EPM9320RC208-10 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | NRND |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 320 | 320 |
| Logic Array Blocks (LABs) | 20 | [DATA_NEEDED: LAB count] |
| Usable Gates | 6,000 | 6,000 |
| Maximum I/O Pins | 132 | — |
| Propagation Delay (tPD max) | 20 ns | — |
| Supply Voltage (VCCINT) | 4.75 V to 5.25 V | — |
| Programming Technology | EEPROM, in-system programmable (ISP) | — |
| Boundary-Scan Interface | IEEE Std. 1149.1 (JTAG) | — |
| Operating Temperature | 0 °C to 70 °C (commercial) | Commercial (0C to +70C) - 'C' suffix |
| Package | 208-RQFP, exposed pad (208-BFQFP) | 208-pin RQFP (RC) |
| Mounting Type | Surface Mount | — |
| Architecture | Multiple Array Matrix (MAX), 3rd generation | — |
| Process Technology | CMOS, 5.0 V EEPROM | — |
| Reprogrammability | Yes, unlimited ISP cycles | — |
| Supply Voltage | — | 5 V |
| Speed Grade | — | -10 |
| Programming Interface | — | JTAG (ByteBlaster/BitBlaster) |
| Non-volatile Configuration | — | Yes (EPROM/EEPROM based) |
| Design Tool Support | — | MAX+PLUS II, Quartus (legacy) |
| RoHS Status | — | ROHS3 Compliant (per fpgalink listing) |
| Moisture Sensitivity Level (MSL) | — | 3 (168 Hours) |
| Lead Time | — | 1-7 days (per fpgalink listing) |