EPM9320RI208-20N vs EPM9320RC208-15 Comparison

Detailed side-by-side comparison of EPM9320RI208-20N by Altera and EPM9320RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9320RI208-20N EPM9320RC208-15
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status NRND Obsolete
Device Family MAX 9000 (EPM9320) MAX 9000
Logic Type EEPROM-based Complex Programmable Logic Device (CPLD) —
Macrocells 320 —
Flip-Flops 484 —
Propagation Delay (tPD) 20 ns —
Supply Voltage (VCC) 5.0 V —
I/O Voltage Tolerance 3.3 V or 5 V configurable —
Package 208-pin PQFP (Plastic Quad Flat Pack) 208-pin RQFP (Power QFP)
Package Lead Pitch 0.500 mm —
Number of Terminals 208 —
Operating Temperature Range -40C to +85C (Industrial) —
In-System Programmability Yes, 5.0 V ISP via JTAG Yes (ISP via JTAG)
JTAG Interface IEEE Std. 1149.1 compliant IEEE Std. 1149.1
Configuration Memory EEPROM (non-volatile) —
Dedicated Input Pins 4 (low-skew global distribution) —
Minimum DC Input on I/O Pins -0.5 V —
Minimum DC Input on Dedicated Inputs -0.3 V —
Input Undershoot/ Overshoot -2.0 V / 7.0 V for <20 ns (no-load) —
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Macro Cells — 320
Usable Gates — 6,000
Pin-to-Pin Propagation Delay — 15 ns (speed grade -15)
Maximum Clock Frequency — 117.6 MHz
Supply Voltage — 5.0 V
Configuration Technology — EEPROM-based (non-volatile)
Package Type — 208-BFQFP Exposed Pad
Operating Temperature — [DATA_NEEDED: operating temperature range]
Number of I/O Pins — [DATA_NEEDED: user I/O count]
Logic Array Blocks — [DATA_NEEDED: LAB count]
Lifecycle Status — Obsolete (PDN0706, 2007)

Datasheets & Resources

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