EPM9320RI208-20N - MAX 9000 CPLD 320 Macrocell 208-PQFP | Altera
MPN: EPM9320RI208-20N ✗ End of Life| Qty | Unit Price | Extended |
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| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
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Drop-in alternatives for EPM9320RI208-20N — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9320RI208-20
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$18.95 / Unit
View Datasheet →EPM9320RI208-10N
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View Datasheet →EPM9320RC208-20N
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View Datasheet →EPM9320RC208-20
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$21.9 / Unit
View Datasheet →EPM9320RC208-15N
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View Datasheet →EPM9320RC208-15
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View Datasheet →EPM9320RI208-20N Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 (EPM9320) |
| Logic Type | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macrocells | 320 |
| Flip-Flops | 484 |
| Propagation Delay (tPD) | 20 ns |
| Supply Voltage (VCC) | 5.0 V |
| I/O Voltage Tolerance | 3.3 V or 5 V configurable |
| Package | 208-pin PQFP (Plastic Quad Flat Pack) |
| Package Lead Pitch | 0.500 mm |
| Number of Terminals | 208 |
| Operating Temperature Range | -40C to +85C (Industrial) |
| In-System Programmability | Yes, 5.0 V ISP via JTAG |
| JTAG Interface | IEEE Std. 1149.1 compliant |
| Configuration Memory | EEPROM (non-volatile) |
| Dedicated Input Pins | 4 (low-skew global distribution) |
| Minimum DC Input on I/O Pins | -0.5 V |
| Minimum DC Input on Dedicated Inputs | -0.3 V |
| Input Undershoot/ Overshoot | -2.0 V / 7.0 V for <20 ns (no-load) |
| Mounting Type | Surface Mount |
EPM9320RI208-20N Pin Configuration
| Pin 1 | I/O — General-purpose I/O pin |
| Pin 2 | I/O — General-purpose I/O pin |
| Pin 3 | I/O — General-purpose I/O pin |
| Pin 4 | I/O — General-purpose I/O pin |
| Pin 5 | I/O — General-purpose I/O pin |
| Pin 6 | I/O — General-purpose I/O pin |
| Pin 7 | I/O — General-purpose I/O pin |
| Pin 8 | I/O — General-purpose I/O pin |
| Pin 9 | I/O — General-purpose I/O pin |
| Pin 10 | I/O — General-purpose I/O pin |
| Pin 11 | I/O — General-purpose I/O pin |
| Pin 12 | I/O — General-purpose I/O pin |
| Pin 13 | I/O — General-purpose I/O pin |
| Pin 14 | I/O — General-purpose I/O pin |
| Pin 15 | I/O — General-purpose I/O pin |
| Pin 16 | I/O — General-purpose I/O pin |
| Pin 17 | I/O — General-purpose I/O pin |
| Pin 18 | I/O — General-purpose I/O pin |
| Pin 19 | I/O — General-purpose I/O pin |
| Pin 20 | I/O — General-purpose I/O pin |
| Pin 21 | I/O — General-purpose I/O pin |
| Pin 22 | I/O — General-purpose I/O pin |
| Pin 23 | I/O — General-purpose I/O pin |
| Pin 24 | I/O — General-purpose I/O pin |
| Pin 25 | I/O — General-purpose I/O pin |
| Pin 26 | I/O — General-purpose I/O pin |
| Pin 27 | I/O — General-purpose I/O pin |
| Pin 28 | I/O — General-purpose I/O pin |
| Pin 29 | I/O — General-purpose I/O pin |
| Pin 30 | I/O — General-purpose I/O pin |
| Pin 31 | I/O — General-purpose I/O pin |
| Pin 32 | I/O — General-purpose I/O pin |
| Pin 33 | I/O — General-purpose I/O pin |
| Pin 34 | I/O — General-purpose I/O pin |
| Pin 35 | I/O — General-purpose I/O pin |
| Pin 36 | I/O — General-purpose I/O pin |
| Pin 37 | I/O — General-purpose I/O pin |
| Pin 38 | I/O — General-purpose I/O pin |
| Pin 39 | I/O — General-purpose I/O pin |
| Pin 40 | I/O — General-purpose I/O pin |
| Pin 41 | I/O — General-purpose I/O pin |
| Pin 42 | I/O — General-purpose I/O pin |
| Pin 43 | I/O — General-purpose I/O pin |
| Pin 44 | I/O — General-purpose I/O pin |
| Pin 45 | I/O — General-purpose I/O pin |
| Pin 46 | I/O — General-purpose I/O pin |
| Pin 47 | I/O — General-purpose I/O pin |
| Pin 48 | I/O — General-purpose I/O pin |
| Pin 49 | I/O — General-purpose I/O pin |
| Pin 50 | I/O — General-purpose I/O pin |
| Pin 51 | I/O — General-purpose I/O pin |
| Pin 52 | I/O — General-purpose I/O pin |
| Pin 53 | GND — Ground |
| Pin 54 | VCC — 5.0 V power supply |
| Pin 55 | I/O — General-purpose I/O pin |
| Pin 56 | I/O — General-purpose I/O pin |
| Pin 57 | I/O — General-purpose I/O pin |
| Pin 58 | I/O — General-purpose I/O pin |
| Pin 59 | I/O — General-purpose I/O pin |
| Pin 60 | I/O — General-purpose I/O pin |
| Pin 61 | I/O — General-purpose I/O pin |
| Pin 62 | I/O — General-purpose I/O pin |
| Pin 63 | I/O — General-purpose I/O pin |
| Pin 64 | I/O — General-purpose I/O pin |
| Pin 65 | I/O — General-purpose I/O pin |
| Pin 66 | I/O — General-purpose I/O pin |
| Pin 67 | I/O — General-purpose I/O pin |
| Pin 68 | I/O — General-purpose I/O pin |
| Pin 69 | I/O — General-purpose I/O pin |
| Pin 70 | I/O — General-purpose I/O pin |
| Pin 71 | I/O — General-purpose I/O pin |
| Pin 72 | I/O — General-purpose I/O pin |
| Pin 73 | I/O — General-purpose I/O pin |
| Pin 74 | I/O — General-purpose I/O pin |
| Pin 75 | I/O — General-purpose I/O pin |
| Pin 76 | I/O — General-purpose I/O pin |
| Pin 77 | I/O — General-purpose I/O pin |
| Pin 78 | I/O — General-purpose I/O pin |
| Pin 79 | I/O — General-purpose I/O pin |
| Pin 80 | I/O — General-purpose I/O pin |
| Pin 81 | I/O — General-purpose I/O pin |
| Pin 82 | I/O — General-purpose I/O pin |
| Pin 83 | I/O — General-purpose I/O pin |
| Pin 84 | I/O — General-purpose I/O pin |
| Pin 85 | I/O — General-purpose I/O pin |
| Pin 86 | I/O — General-purpose I/O pin |
| Pin 87 | I/O — General-purpose I/O pin |
| Pin 88 | I/O — General-purpose I/O pin |
| Pin 89 | I/O — General-purpose I/O pin |
| Pin 90 | I/O — General-purpose I/O pin |
| Pin 91 | I/O — General-purpose I/O pin |
| Pin 92 | I/O — General-purpose I/O pin |
| Pin 93 | I/O — General-purpose I/O pin |
| Pin 94 | I/O — General-purpose I/O pin |
| Pin 95 | I/O — General-purpose I/O pin |
| Pin 96 | I/O — General-purpose I/O pin |
| Pin 97 | I/O — General-purpose I/O pin |
| Pin 98 | I/O — General-purpose I/O pin |
| Pin 99 | I/O — General-purpose I/O pin |
| Pin 100 | I/O — General-purpose I/O pin |
| Pin 101 | I/O — General-purpose I/O pin |
| Pin 102 | I/O — General-purpose I/O pin |
| Pin 103 | I/O — General-purpose I/O pin |
| Pin 104 | I/O — General-purpose I/O pin |
| Pin 105 | GND — Ground |
| Pin 106 | VCC — 5.0 V power supply |
| Pin 107 | I/O — General-purpose I/O pin |
| Pin 108 | I/O — General-purpose I/O pin |
| Pin 109 | I/O — General-purpose I/O pin |
| Pin 110 | I/O — General-purpose I/O pin |
| Pin 111 | I/O — General-purpose I/O pin |
| Pin 112 | I/O — General-purpose I/O pin |
| Pin 113 | I/O — General-purpose I/O pin |
| Pin 114 | I/O — General-purpose I/O pin |
| Pin 115 | I/O — General-purpose I/O pin |
| Pin 116 | I/O — General-purpose I/O pin |
| Pin 117 | I/O — General-purpose I/O pin |
| Pin 118 | I/O — General-purpose I/O pin |
| Pin 119 | I/O — General-purpose I/O pin |
| Pin 120 | I/O — General-purpose I/O pin |
| Pin 121 | I/O — General-purpose I/O pin |
| Pin 122 | I/O — General-purpose I/O pin |
| Pin 123 | I/O — General-purpose I/O pin |
| Pin 124 | I/O — General-purpose I/O pin |
| Pin 125 | I/O — General-purpose I/O pin |
| Pin 126 | I/O — General-purpose I/O pin |
| Pin 127 | I/O — General-purpose I/O pin |
| Pin 128 | I/O — General-purpose I/O pin |
| Pin 129 | I/O — General-purpose I/O pin |
| Pin 130 | I/O — General-purpose I/O pin |
| Pin 131 | I/O — General-purpose I/O pin |
| Pin 132 | I/O — General-purpose I/O pin |
| Pin 133 | I/O — General-purpose I/O pin |
| Pin 134 | I/O — General-purpose I/O pin |
| Pin 135 | I/O — General-purpose I/O pin |
| Pin 136 | I/O — General-purpose I/O pin |
| Pin 137 | I/O — General-purpose I/O pin |
| Pin 138 | I/O — General-purpose I/O pin |
| Pin 139 | I/O — General-purpose I/O pin |
| Pin 140 | I/O — General-purpose I/O pin |
| Pin 141 | I/O — General-purpose I/O pin |
| Pin 142 | I/O — General-purpose I/O pin |
| Pin 143 | I/O — General-purpose I/O pin |
| Pin 144 | I/O — General-purpose I/O pin |
| Pin 145 | I/O — General-purpose I/O pin |
| Pin 146 | I/O — General-purpose I/O pin |
| Pin 147 | I/O — General-purpose I/O pin |
| Pin 148 | I/O — General-purpose I/O pin |
| Pin 149 | I/O — General-purpose I/O pin |
| Pin 150 | I/O — General-purpose I/O pin |
| Pin 151 | I/O — General-purpose I/O pin |
| Pin 152 | I/O — General-purpose I/O pin |
| Pin 153 | I/O — General-purpose I/O pin |
| Pin 154 | I/O — General-purpose I/O pin |
| Pin 155 | I/O — General-purpose I/O pin |
| Pin 156 | I/O — General-purpose I/O pin |
| Pin 157 | GND — Ground |
| Pin 158 | VCC — 5.0 V power supply |
| Pin 159 | I/O — General-purpose I/O pin |
| Pin 160 | I/O — General-purpose I/O pin |
| Pin 161 | I/O — General-purpose I/O pin |
| Pin 162 | I/O — General-purpose I/O pin |
| Pin 163 | I/O — General-purpose I/O pin |
| Pin 164 | I/O — General-purpose I/O pin |
| Pin 165 | I/O — General-purpose I/O pin |
| Pin 166 | I/O — General-purpose I/O pin |
| Pin 167 | I/O — General-purpose I/O pin |
| Pin 168 | I/O — General-purpose I/O pin |
| Pin 169 | I/O — General-purpose I/O pin |
| Pin 170 | I/O — General-purpose I/O pin |
| Pin 171 | I/O — General-purpose I/O pin |
| Pin 172 | I/O — General-purpose I/O pin |
| Pin 173 | I/O — General-purpose I/O pin |
| Pin 174 | I/O — General-purpose I/O pin |
| Pin 175 | I/O — General-purpose I/O pin |
| Pin 176 | I/O — General-purpose I/O pin |
| Pin 177 | I/O — General-purpose I/O pin |
| Pin 178 | I/O — General-purpose I/O pin |
| Pin 179 | I/O — General-purpose I/O pin |
| Pin 180 | I/O — General-purpose I/O pin |
| Pin 181 | I/O — General-purpose I/O pin |
| Pin 182 | I/O — General-purpose I/O pin |
| Pin 183 | I/O — General-purpose I/O pin |
| Pin 184 | I/O — General-purpose I/O pin |
| Pin 185 | I/O — General-purpose I/O pin |
| Pin 186 | I/O — General-purpose I/O pin |
| Pin 187 | I/O — General-purpose I/O pin |
| Pin 188 | I/O — General-purpose I/O pin |
| Pin 189 | I/O — General-purpose I/O pin |
| Pin 190 | I/O — General-purpose I/O pin |
| Pin 191 | I/O — General-purpose I/O pin |
| Pin 192 | I/O — General-purpose I/O pin |
| Pin 193 | I/O — General-purpose I/O pin |
| Pin 194 | I/O — General-purpose I/O pin |
| Pin 195 | I/O — General-purpose I/O pin |
| Pin 196 | I/O — General-purpose I/O pin |
| Pin 197 | I/O — General-purpose I/O pin |
| Pin 198 | I/O — General-purpose I/O pin |
| Pin 199 | I/O — General-purpose I/O pin |
| Pin 200 | I/O — General-purpose I/O pin |
| Pin 201 | I/O — General-purpose I/O pin |
| Pin 202 | I/O — General-purpose I/O pin |
| Pin 203 | I/O — General-purpose I/O pin |
| Pin 204 | I/O — General-purpose I/O pin |
| Pin 205 | I/O — General-purpose I/O pin |
| Pin 206 | I/O — General-purpose I/O pin |
| Pin 207 | I/O — General-purpose I/O pin |
| Pin 208 | I/O — General-purpose I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9320RI208-20N is suitable for 6 applications: Legacy Glue Logic Replacement, Industrial Control State Machines, Bus Interface and Protocol Bridging, Instrumentation Front-End Logic, Telecommunications Line Card Control, Military and Aerospace Legacy Upgrades.
Legacy Glue Logic Replacement
The EPM9320RI208-20N is widely used to consolidate dozens of discrete 74-series logic ICs into a single 208-pin PQFP device. Its 320 macrocells and 484 flip-flops can absorb address decoding, bus arbitration, and control-signal generation that previously required multiple boards. The 20 ns pin-to-pin delay is deterministic and guaranteed, unlike SRAM-based FPGAs, so worst-case timing analysis remains straightforward. Because configuration is stored in on-chip EEPROM, the device is instant-on at power-up with no external boot PROM, which is critical for legacy systems that must not add a configuration delay. Designers typically map existing 74LS/74F logic equations directly into the MAX 9000 architecture using Altera's MAX+PLUS II toolchain, preserving the original timing budget while reducing board area and component count.
Recommended
Industrial Control State Machines
The EPM9320RI208-20N is well suited to industrial control state machines because its industrial temperature rating of -40C to +85C covers factory-floor and outdoor environments. The 484 flip-flops allow complex multi-state sequencers to be implemented entirely on-chip, while the 20 ns propagation delay guarantees deterministic state-transition timing. The four dedicated low-skew input pins distribute global clock, clear, and output-enable signals across all Logic Array Blocks, minimizing clock skew in synchronous designs. EEPROM configuration means the state machine resumes its programmed behavior immediately after a power interruption, without the reconfiguration latency of SRAM-based devices. Typical implementations include conveyor sequencing, valve and actuator control, and safety interlock logic in PLC-adjacent subsystems.
Recommended
Bus Interface and Protocol Bridging
The EPM9320RI208-20N provides up to 160 user I/O pins in its 208-pin PQFP package, making it effective for wide bus interface and protocol bridging tasks. Its 3.3 V or 5 V configurable I/O allows it to sit between legacy 5 V peripherals and 3.3 V host controllers, translating voltage levels and bus protocols in a single device. The 20 ns pin-to-pin delay supports bus cycle times down to roughly 50 MHz for simple combinatorial paths, adequate for ISA, PC/104, and similar legacy buses. Designers implement address decoding, wait-state generation, and handshake logic in the programmable array, replacing discrete transceivers and PALs. The non-volatile EEPROM configuration ensures the bridge logic is active from the first clock edge after power-up, avoiding bus contention during system initialization.
Recommended
Instrumentation Front-End Logic
In test and measurement instruments, the EPM9320RI208-20N handles front-end control logic such as trigger generation, sample-clock sequencing, and ADC/DAC interface timing. The 20 ns deterministic delay allows precise placement of trigger and conversion-start edges relative to the sample clock, which directly affects measurement jitter. The 484 flip-flops support multi-channel sample counters and FIFO control without external logic. Because the device is EEPROM-configured, it powers up in a known state, which is important for instruments that must be ready immediately after power-on. The industrial temperature range supports benchtop and rack-mount instruments operating in non-climate-controlled environments. Designers often pair the CPLD with precision analog front-ends to implement programmable gain and channel-selection sequencing.
Recommended
Telecommunications Line Card Control
The EPM9320RI208-20N is used on telecommunications line cards for local control functions such as timeslot assignment, framer interface logic, and alarm monitoring. Its 320 macrocells can implement per-channel control state machines for multiple T1/E1 or similar line interfaces, while the 208-pin package provides enough I/O to connect to framers, line drivers, and backplane connectors. The 5.0 V supply and 3.3 V/5 V configurable I/O match the mixed-voltage environment typical of telecom equipment. Deterministic 20 ns timing simplifies worst-case timing analysis for the control path, and EEPROM configuration ensures the line card is operational immediately after power restoration, which is essential for carrier-grade availability requirements.
Recommended
Military and Aerospace Legacy Upgrades
The EPM9320RI208-20N is sometimes selected for military and aerospace legacy upgrades where an existing MAX 9000 design must be maintained or reproduced. Its industrial temperature range of -40C to +85C covers many ground-vehicle and avionics-bay environments, though it is not a radiation-hardened or full military-temperature part. The EEPROM configuration provides instant-on operation and immunity to single-event configuration upsets that affect SRAM FPGAs. The 20 ns deterministic delay supports repeatable timing in control and interface logic. Engineers performing form-fit-function replacement of obsolete boards often choose this device because the MAX 9000 architecture and MAX+PLUS II design flow are well documented, reducing requalification effort compared with migrating to a modern FPGA.
Recommended
Recommended Products Summary
Engineering reference data for EPM9320RI208-20N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9320RI208-20 | EPM9320RI208-10N | EPM9320RC208-20N | EPM9320RC208-15N |
|---|---|---|---|---|---|
| Package | 208-pin PQFP | 208-pin PQFP - same | 208-pin PQFP - same | 208-pin PQFP - same | 208-pin PQFP - same |
| Brand | Altera | Altera | Altera | Altera | Altera |
| Propagation Delay (tPD) | 20 ns | 20 ns | 10 ns | 20 ns | 15 ns |
| Macrocells | 320 | 320 | 320 | 320 | 320 |
| Flip-Flops | 484 | 484 | 484 | 484 | 484 |
| Temperature Grade | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Industrial (-40C to +85C) | Commercial (0C to +70C) | Commercial (0C to +70C) |
| Supply Voltage (VCC) | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| In-System Programmability | Yes (5.0 V ISP via JTAG) | Yes (5.0 V ISP via JTAG) | Yes (5.0 V ISP via JTAG) | Yes (5.0 V ISP via JTAG) | Yes (5.0 V ISP via JTAG) |
| Configuration Memory | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Lead Finish | Lead-free (N suffix) | Leaded (non-N) | Lead-free (N suffix) | Lead-free (N suffix) | Lead-free (N suffix) |
Key Differentiators
- Industrial temperature range with lead-free finish (vs EPM9320RC208-20N)
- 20 ns speed grade at lower cost than 10 ns variant (vs EPM9320RI208-10N)
- Lead-free (N) package finish (vs EPM9320RI208-20)
- Deterministic 20 ns timing versus SRAM FPGA alternatives (vs EPM9320RC208-15N)
Design Notes
VCC must rise monotonically during power-up to guarantee correct EEPROM configuration loading. According to the MAX 9000 datasheet, a non-monotonic ramp can leave the device in an indeterminate state. Use a power-supply supervisor or RC network to ensure a clean 5.0 V ramp. Decouple each VCC pin with a 0.1 uF ceramic capacitor placed within 5 mm of the pin, plus a bulk 10 uF capacitor per device. Estimated: at 5.0 V and typical ICC of a few hundred mA, total decoupling should support transient currents without exceeding 50 mV ripple.
The four dedicated input pins provide low-skew, device-wide distribution for global clock, clear, and output-enable signals. Route these signals as controlled-impedance traces (50 ohm) and keep stub lengths under 10 mm to preserve the low-skew benefit. Do not use general-purpose I/O pins for global clocks, as they route through the programmable interconnect and add delay and skew. Terminate unused dedicated inputs to GND or VCC through a resistor rather than leaving them floating.
Inputs may undershoot to -2.0 V or overshoot to 7.0 V for periods shorter than 20 ns under no-load conditions, but sustained excursions beyond the -0.5 V (I/O) or -0.3 V (dedicated input) minimum DC limits will damage the device. Add series termination resistors (22-33 ohm) on fast-edge signals that drive long traces. Also verify that the JTAG TCK, TMS, TDI, and TDO pins are not loaded by other devices on the scan chain in a way that violates setup/hold timing during ISP.
The 208-pin PQFP package dissipates heat primarily through the package body and leads. Estimated: at 5.0 V and 300 mA ICC, power dissipation is approximately 1.5 W. With a typical theta_JA of 30-40 C/W for a 208-pin PQFP on a multi-layer board, junction temperature rise is roughly 45-60 C above ambient. In a 70 C ambient environment this approaches the 85 C industrial limit, so provide adequate copper area on the VCC and GND planes and ensure airflow in enclosed cabinets.
Place the device centrally on the board to minimize trace lengths to connected peripherals. Keep the JTAG header close to the CPLD and route TCK as a controlled-impedance trace away from noisy switching signals. Use a solid ground plane under the device and avoid routing high-speed signals beneath the package. For the 0.5 mm lead pitch, use a stencil with adequate paste release and verify solder-joint quality with X-ray inspection, as fine-pitch PQFP assembly is prone to bridging.
Compliance Information
The 'N' suffix in Altera part numbering typically denotes a lead-free package variant, but RoHS/REACH compliance was not confirmed in the retrieved web data. Verify with the manufacturer or distributor certificate of compliance before design-in. AEC-Q100 is not applicable to this industrial-grade CPLD.
