EPM9480RC208-15 vs EPM9320RC208-20 Comparison
Detailed side-by-side comparison of EPM9480RC208-15 by Intel and EPM9320RC208-20 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9480RC208-15 | EPM9320RC208-20 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Logic Cells / Macro Cells | 480 macro cells | — |
| Usable Gates | 10,000 gates | 6,000 |
| Maximum Operating Frequency | 117.6 MHz | — |
| Propagation Delay (tPD) | 15 ns | — |
| User I/O Pins | 153 | — |
| Supply Voltage | 5.0 V | — |
| Programmability | In-System (ISP) via JTAG IEEE 1149.1 | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Package | RQFP-208 | 208-RQFP, exposed pad (208-BFQFP) |
| Operating Temperature | -40C to +85C (commercial) | 0 °C to 70 °C (commercial) |
| Mounting Type | Surface Mount | Surface Mount |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation | Multiple Array Matrix (MAX), 3rd generation |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | — |
| MSL Level | [DATA_NEEDED: MSL rating] | — |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 320 |
| Logic Array Blocks (LABs) | — | 20 |
| Maximum I/O Pins | — | 132 |
| Propagation Delay (tPD max) | — | 20 ns |
| Supply Voltage (VCCINT) | — | 4.75 V to 5.25 V |
| Programming Technology | — | EEPROM, in-system programmable (ISP) |
| Boundary-Scan Interface | — | IEEE Std. 1149.1 (JTAG) |
| Process Technology | — | CMOS, 5.0 V EEPROM |
| Reprogrammability | — | Yes, unlimited ISP cycles |