EPM9560ARC240-10 vs EPM9560ABC356-10 Comparison

Detailed side-by-side comparison of EPM9560ARC240-10 by Altera and EPM9560ABC356-10 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560ARC240-10 EPM9560ABC356-10
Brand Altera Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Nrnd
Stock Status In Stock In Stock
Unit Price (USD) $28.80 $92.40
Family MAX 9000 β€”
Device Type CPLD (Complex Programmable Logic Device) β€”
Architecture Multiple Array MatriX (MAX) - third generation β€”
Usable Gates 12,000 12,000
Macrocells 560 560
User I/Os (this package) 191 (per Mouser listing) β€”
Internal Frequency 144.9 MHz β€”
Propagation Delay (tpd) 11.4 ns β€”
Supply Voltage - Internal (VCCINT) 5.0 V β€”
I/O Supply Voltage (VCCIO) 3.3 V or 5.0 V (selectable) β€”
Process Technology CMOS EEPROM β€”
Package 240-pin PowerQuad QFP (RQFP / EAR240) 356-LBGA (35 x 35 mm)
Operating Temperature 0C to +70C (commercial) 0 Β°C to 70 Β°C (Commercial)
Configuration Memory EEPROM (non-volatile, in-system programmable) β€”
Logic Family CMOS β€”
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: rohs status]
Device Family β€” MAX 9000A
Product Series β€” MAX 9000
Logic Array Blocks (LABs) β€” 35
Maximum User I/Os β€” 216
Pin-to-Pin Delay (tPD) β€” 10 ns
Maximum Counter Frequency β€” 144 MHz
Supply Voltage β€” 4.75 V to 5.25 V (5 V nominal)
Programmability β€” EEPROM, 5-V In-System Programmable (ISP)
JTAG Interface β€” IEEE Std. 1149.1 compliant
PCI Compliance β€” PCI Local Bus Specification Revision 2.2
Mounting Type β€” Surface Mount

Datasheets & Resources

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