EPM9560ARC240-10 vs EPM9560RC-10 Comparison
Detailed side-by-side comparison of EPM9560ARC240-10 by Altera and EPM9560RC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560ARC240-10 | EPM9560RC-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | CPLD (Complex Programmable Logic Device) |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array Matrix (MAX) - third generation |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| User I/Os (this package) | 191 (per Mouser listing) | — |
| Internal Frequency | 144.9 MHz | — |
| Propagation Delay (tpd) | 11.4 ns | — |
| Supply Voltage - Internal (VCCINT) | 5.0 V | — |
| I/O Supply Voltage (VCCIO) | 3.3 V or 5.0 V (selectable) | — |
| Process Technology | CMOS EEPROM | CMOS EEPROM |
| Package | 240-pin PowerQuad QFP (RQFP / EAR240) | 240-pin PGA (RC suffix) |
| Operating Temperature | 0C to +70C (commercial) | 0C to +70C (commercial) |
| Configuration Memory | EEPROM (non-volatile, in-system programmable) | — |
| Logic Family | CMOS | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | unknown |
| Logic Array Blocks (LABs) | — | 16 |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| In-System Programmability | — | IEEE 1149.1 JTAG |
| Mounting Type | — | Through-Hole / Socketed |