EPM9560RC-10 - MAX 9000 CPLD, 560 Macrocells, 240-pin PGA | Intel
MPN: EPM9560RC-10 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $165 | $1,650.00 |
| 100 | $140 | $14,000.00 |
| 250 | $125 | $31,250.00 |
| 500 | $110 | $55,000.00 |
Drop-in alternatives for EPM9560RC-10 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560ARC240-10
✅ Drop-In✓ In Stock
$28.8 / Unit
View Datasheet →EPM9560ARC240-10N
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$19.5 / Unit
View Datasheet →EPM9560ARI240-10
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Contact for price
View Datasheet →EPM9560ARI240-10N
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$105 / Unit
View Datasheet →EPM9560RC-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O Pins | 212 |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V |
| In-System Programmability | IEEE 1149.1 JTAG |
| Process Technology | CMOS EEPROM |
| Architecture | Multiple Array Matrix (MAX) - third generation |
| Operating Temperature | 0C to +70C (commercial) |
| Package | 240-pin PGA (RC suffix) |
| Mounting Type | Through-Hole / Socketed |
| RoHS Status | unknown |
EPM9560RC-10 240-pin pga (rc suffix) Pin Configuration Guide
Complete pinout information for EPM9560RC-10 (240-pin pga (rc suffix) package) with 212 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC-10.
Refer to the datasheet for full pin configuration.
Estimated pin count: 212 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC-10 is suitable for 6 applications: High-Performance Bus Interface Bridging, Processor Glue Logic and Address Decoding, State-Machine and Protocol Controllers, Legacy Telecom Backplane Logic, Industrial Automation Controllers, Aerospace and Defense Prototype Systems.
High-Performance Bus Interface Bridging
The EPM9560RC-10's 560 macrocells and 212 user I/Os make it ideal for bridging between disparate processor buses in legacy industrial and telecom systems. Its 10 ns tPD allows glue-logic interfaces between 32-bit microprocessors, memory controllers, and peripheral buses without adding wait states. The 5.0 V tolerance matches TTL/CMOS logic levels common in older backplane designs, and the non-volatile EEPROM configuration means zero boot latency. Compared to FPGAs, the MAX 9000 architecture provides deterministic timing - critical for bus-arbiter and handshake logic where races would corrupt data. Place the device near the bus connectors and decouple every VCCINT/VCCIO pair with 0.1 uF ceramics.
Recommended
Processor Glue Logic and Address Decoding
With 16 LABs and a robust product-term allocator, the EPM9560RC-10 efficiently implements address decoding, chip-select generation, and wait-state insertion for legacy microprocessors such as the 80x86, 68k, and MIPS families. Its 10 ns propagation delay supports zero-wait-state designs up to ~50 MHz, while 212 I/Os accommodate wide address and data buses plus peripheral control signals. The JTAG ISP interface simplifies board bring-up, allowing engineers to iterate on decode logic without removing the device. Place a 10 kohm pull-up on the JTAG TMS line for clean boundary-scan operation.
Recommended
State-Machine and Protocol Controllers
Each macrocell in the EPM9560RC-10 supports a programmable D/T/JK flip-flop and 32 product terms, making the device exceptionally well-suited to large synchronous state machines implementing serial protocols (UART, SPI, I2C), custom peripheral controllers, and sequencing engines. The deterministic MAX interconnect ensures that every state transition completes within a known timing window, eliminating the metastability concerns that plague SRAM-based FPGA designs. Designers can partition complex protocols across multiple LABs while preserving 10 ns-class timing margins for 25-50 Mbps serial links.
Recommended
Legacy Telecom Backplane Logic
The EPM9560RC-10's 240-pin ceramic PGA package and 5.0 V tolerance make it a natural fit for legacy telecom backplanes that use TTL bus standards and socketed through-hole components for field serviceability. Its 12,000 usable gates and 212 I/Os can replace multiple 22V10/26V12 PALs and discrete MSI logic, simplifying board layout and improving reliability. The ceramic PGA withstands the wider thermal and mechanical environments of central-office equipment. JTAG ISP enables in-field reconfiguration when protocol updates are required.
Recommended
Industrial Automation Controllers
In industrial PLC and motor-control subsystems, the EPM9560RC-10 can replace dozens of discrete logic ICs by integrating encoder decoding, PWM generation, fault handling, and safety interlocks into a single non-volatile device. The 10 ns tPD supports real-time control loops, while the 212 I/Os interface directly to 5 V sensors, optocouplers, and H-bridge drivers. Its deterministic timing avoids the variable-latency issues of microcontrollers running RTOS code, making it ideal for hard-real-time sequencing. Designers should observe derating guidelines for I/O current and add external buffers for high-current loads.
Recommended
Aerospace and Defense Prototype Systems
The ceramic PGA package of the EPM9560RC-10 provides the mechanical robustness and thermal performance required for aerospace and defense prototype systems, where socketed CPLDs simplify iterative design and qualification testing. Its 12,000-gate density and 10 ns speed are sufficient for flight-control signal conditioning, sensor-fusion glue logic, and MIL-STD-1553 interface bridging. The non-volatile EEPROM configuration eliminates the need for separate boot PROMs, reducing BOM and improving reliability. Designers should verify radiation-hardness and trace documentation before flight deployment.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC-10 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560ARC240-10 | EPM9560ARC240-10N | EPM9560ARI240-10 | EPM9560ARI240-10N |
|---|---|---|---|---|---|
| Package | 240-pin Ceramic PGA | 240-pin Plastic PGA - same footprint | 240-pin Plastic PGA - same footprint | 240-pin Plastic PGA - same footprint | 240-pin Plastic PGA - same footprint |
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Macrocells | 560 | 560 | 560 | 560 | 560 |
| Speed Grade (tPD) | 10 ns | 10 ns | 10 ns | 10 ns | 10 ns |
| Temperature Grade | Commercial (0C to +70C) | Commercial (0C to +70C) | Commercial (0C to +70C), lead-free | Industrial (-40C to +85C) | Industrial (-40C to +85C), lead-free |
| Package Material | Ceramic | Plastic | Plastic | Plastic | Plastic |
| Lead-Free (N suffix) | Unknown | No | Yes | No | Yes |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Ceramic PGA package for high-reliability and socketed serviceability (vs EPM9560ABC356-10)
- Highest macrocell density in the MAX 9000 family at 560 macrocells (vs EPM9480RC240-20)
- Commercial temperature grade for cost-sensitive applications (vs EPM9560ARI240-10)
Design Notes
The EPM9560RC-10 requires 5.0 V on both VCCINT (core) and VCCIO (I/O) supply pins. Decouple every VCC/VSS pair with a 0.1 uF X7R ceramic capacitor placed within 5 mm of the pin, and add a bulk 10-47 uF tantalum or aluminum polymer capacitor near the device. The MAX 9000 datasheet recommends one decoupling capacitor per power pin pair to suppress switching noise during simultaneous I/O toggling. The device draws approximately 200-400 mA quiescent current depending on logic utilization and toggle rate; size the regulator accordingly.
The 240-pin ceramic PGA package requires a PGA socket (e.g., a machine-pin socket) for through-hole PCB mounting. Ensure the socket footprint on the PCB matches the standard 240-pin PGA land pattern (24x24 grid with 2.54 mm pitch) and that adequate clearance exists around the socket for the device's ceramic body and heatsink attachment if needed. The ceramic package provides good thermal conductivity (~15 C/W theta_JC), but thermal performance still benefits from a copper heatsink or airflow above 50% macrocell utilization.
Do not assume that any MAX 9000 device with the same speed grade is a drop-in replacement for the EPM9560RC-10 - the package suffix matters. The 'RC' suffix denotes the 240-pin ceramic PGA, while 'ARI240' denotes a 240-pin plastic PGA industrial variant, and 'ABC356' denotes a 356-ball BGA. PCB redesign is required to switch between these packages. Also, note that the -10 speed grade (10 ns tPD) differs from -15 and -20 grades; substituting a slower grade will violate timing budgets. Always check the full MPN including package and speed suffixes.
Compliance Information
RoHS and lead-free status not explicitly stated in the verified web data. The 'N' suffix in related part numbers (e.g., EPM9560ARC240-10N) indicates a lead-free variant; the EPM9560RC-10 base part number does not carry the N suffix, suggesting it may use SnPb finish consistent with ceramic PGA packaging of that era. Buyers should request a Certificate of Compliance from the distributor for production orders.
