EPM9560ARI208-10 vs EPM9560ARI208-10N Comparison
Detailed side-by-side comparison of EPM9560ARI208-10 by Intel and EPM9560ARI208-10N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Altera
EPM9560ARI208-10N - MAX 9000 CPLD 12K Gates 560 Macrocells | Altera
EPM9560ARI208-10N ObsoleteSpecification Comparison
| Parameter | EPM9560ARI208-10 | EPM9560ARI208-10N |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Macro Cells | 560 | — |
| Usable Gates | 12,000 | 12,000 |
| Propagation Delay | 10 ns | — |
| Maximum Internal Frequency | 144.9 MHz | — |
| User I/O Pins | 153 | — |
| Supply Voltage | 5.0 V | 5.0 V |
| Technology | CMOS EEPROM | — |
| Package | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin RQFP (Plastic) |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | 0 C to +70 C | 0 C to 70 C (Commercial) |
| Logic Family | CMOS | CMOS EEPROM |
| Programmability | In-System Programmable (ISP) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Speed Grade | -10 | — |
| RoHS Status | [DATA_NEEDED: RoHS status] | — |
| Pin Count | 208 | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 560 |
| Logic Array Blocks (LABs) | — | 35 |
| Maximum User I/O Pins | — | 212 |
| Flip-Flops | — | 484 |
| Propagation Delay (tPD1) | — | 10 ns |
| Clock-to-Output (tCO) | — | 4.5 ns |
| Setup Time (tSU) | — | 3.0 ns |
| Maximum Counter Frequency (fCNT) | — | 144.9 MHz |
| Programming Interface | — | JTAG (IEEE 1149.1) - In-System Programmable |