EPM9560ARI208-10 vs EPM9560ARI208-10N 比較
詳細並排比較 EPM9560ARI208-10 由 Intel 與 EPM9560ARI208-10N 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
Altera
EPM9560ARI208-10N - MAX 9000 CPLD 12K Gates 560 Macrocells | Altera
EPM9560ARI208-10N Obsolete規格比較
| 參數 | EPM9560ARI208-10 | EPM9560ARI208-10N |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Macro Cells | 560 | — |
| Usable Gates | 12,000 | 12,000 |
| Propagation Delay | 10 ns | — |
| Maximum Internal Frequency | 144.9 MHz | — |
| User I/O Pins | 153 | — |
| 供應電壓 | 5.0 V | 5.0 V |
| Technology | CMOS EEPROM | — |
| 封裝 | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin RQFP (Plastic) |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | 0 C to +70 C | 0 C to 70 C (Commercial) |
| Logic Family | CMOS | CMOS EEPROM |
| Programmability | In-System Programmable (ISP) | — |
| Configuration Memory | EEPROM (non-volatile) | — |
| Speed Grade | -10 | — |
| RoHS 狀態 | [DATA_NEEDED: RoHS status] | — |
| 腳位數 | 208 | — |
| Product Type | — | CPLD (Complex Programmable Logic Device) |
| Macrocells | — | 560 |
| Logic Array Blocks (LABs) | — | 35 |
| Maximum User I/O Pins | — | 212 |
| Flip-Flops | — | 484 |
| Propagation Delay (tPD1) | — | 10 ns |
| Clock-to-Output (tCO) | — | 4.5 ns |
| Setup Time (tSU) | — | 3.0 ns |
| Maximum Counter Frequency (fCNT) | — | 144.9 MHz |
| Programming Interface | — | JTAG (IEEE 1149.1) - In-System Programmable |