EPM9560ARI240-10 vs EPM9560ARI240-10N Comparison

Detailed side-by-side comparison of EPM9560ARI240-10 by Altera and EPM9560ARI240-10N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560ARI240-10 EPM9560ARI240-10N
Brand Altera Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete NRND
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) —
Usable Gates 12,000 12,000
Macro Cells 560 —
User I/O Pins 191 —
Package 240-pin RQFP (PowerQuad Flat Pack) 240-pin RQFP (RQFP-240 / PQFP-240)
Pin-to-Pin Propagation Delay 10 ns —
Internal Frequency 144.9 MHz —
Supply Voltage 5.0 V 5.0 V nominal (4.5 V min, 5.5 V max)
Technology CMOS, EEPROM-based configuration —
Operating Temperature Range -40 C to +85 C (industrial) —
Mounting Type Surface Mount Surface Mount
Configuration Memory EEPROM (non-volatile, instant-on) —
Logic Architecture Multiple Array MatriX (MAX) with global interconnect array —
RoHS Status [DATA_NEEDED: RoHS status] —
Moisture Sensitivity Level [DATA_NEEDED: MSL level] —
Number of Terminals 240 —
Terminal Form Gull Wing —
Product Type — CPLD (Complex Programmable Logic Device)
Macrocells — 560
Logic Array Blocks (LABs) — 16
User I/Os — 216 (per digchip); 191 (per Mouser)
Maximum Internal Frequency — 144.9 MHz (typical); 145 MHz (per digchip)
Propagation Delay (tPD) — 10 ns (-10 speed grade)
Logic Family — CMOS, EEPROM-based
In-System Programmability — Yes (5.0 V ISP via JTAG)
Operating Temperature — -40C to +85C (industrial)
Architecture — Multiple Array MatriX (MAX) - 3rd generation
JTAG (IEEE 1149.1) — Yes
Lead-Free / RoHS — [DATA_NEEDED: lead-free / RoHS status not in provided data]

Datasheets & Resources

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