EPM9560ARI240-10N - MAX 9000 CPLD, 560 Macrocells, 5V, 240-RQFP | Intel
MPN: EPM9560ARI240-10N β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $165 | $165.00 |
| 10 | $148.5 | $1,485.00 |
| 100 | $132 | $13,200.00 |
| 500 | $118 | $59,000.00 |
| 1,000 | $105 | $105,000.00 |
Drop-in alternatives for EPM9560ARI240-10N β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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View Datasheet βEPM9560ARI240-10N Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Product Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 16 |
| User I/Os | 216 (per digchip); 191 (per Mouser) |
| Maximum Internal Frequency | 144.9 MHz (typical); 145 MHz (per digchip) |
| Propagation Delay (tPD) | 10 ns (-10 speed grade) |
| Supply Voltage | 5.0 V nominal (4.5 V min, 5.5 V max) |
| Logic Family | CMOS, EEPROM-based |
| In-System Programmability | Yes (5.0 V ISP via JTAG) |
| Package | 240-pin RQFP (RQFP-240 / PQFP-240) |
| Mounting Type | Surface Mount |
| Operating Temperature | -40C to +85C (industrial) |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation |
| JTAG (IEEE 1149.1) | Yes |
EPM9560ARI240-10N Pin Configuration
| Pin 1 | GND β Ground |
| Pin 2 | I/O β User I/O bank 1 |
| Pin 3 | I/O β User I/O bank 1 |
| Pin 4 | I/O β User I/O bank 1 |
| Pin 5 | VCC β 5.0V supply |
| Pin 6 | I/O β User I/O bank 1 |
| Pin 7 | I/O β User I/O bank 1 |
| Pin 8 | I/O β User I/O bank 1 |
| Pin 9 | GND β Ground |
| Pin 10 | I/O β User I/O bank 1 |
| Pin 11 | I/O β User I/O bank 1 |
| Pin 12 | I/O β User I/O bank 1 |
| Pin 13 | VCC β 5.0V supply |
| Pin 14 | I/O β User I/O bank 1 |
| Pin 15 | I/O β User I/O bank 1 |
| Pin 16 | I/O β User I/O bank 1 |
| Pin 17 | GND β Ground |
| Pin 18 | I/O β User I/O bank 2 |
| Pin 19 | I/O β User I/O bank 2 |
| Pin 20 | I/O β User I/O bank 2 |
| Pin 21 | VCC β 5.0V supply |
| Pin 22 | I/O β User I/O bank 2 |
| Pin 23 | I/O β User I/O bank 2 |
| Pin 24 | I/O β User I/O bank 2 |
| Pin 25 | GND β Ground |
| Pin 26 | I/O β User I/O bank 2 |
| Pin 27 | I/O β User I/O bank 2 |
| Pin 28 | I/O β User I/O bank 2 |
| Pin 29 | VCC β 5.0V supply |
| Pin 30 | I/O β User I/O bank 2 |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560ARI240-10N is suitable for 7 applications: High-Speed Glue Logic and Bus Bridging, State-Machine Controllers, Address Decoding and Wait-State Generation, Interface Translation Between Logic Families, Industrial Control Systems, Telecommunications Backplane Glue, Legacy Hardware Maintenance and Last-Time Buy.
High-Speed Glue Logic and Bus Bridging
The EPM9560ARI240-10N fits high-speed glue logic applications because its 10 ns propagation delay and 144.9 MHz maximum internal frequency deliver deterministic timing across combinational and registered logic paths. The 560 macrocells and 216 user I/Os can absorb large glue-logic functions - address decoding, wait-state generation, bus multiplexing, and PCI-to-local bus bridging - that would otherwise require multiple discrete 74-series logic chips. Placed between a host processor and peripheral bus, the device consolidates dozens of discrete packages into a single reprogrammable IC, reducing board area and inventory. The 5V VCCIO tolerance also interfaces directly with legacy 5V peripherals without level shifters.
Recommended
State-Machine Controllers
The EPM9560ARI240-10N is well suited to complex state-machine controllers because the MAX architecture implements each macrocell as a registered sum-of-products logic block with a flip-flop, giving each macrocell inherent registered state. With 560 macrocells and 16 LABs, the device can implement multiple concurrent state machines of up to 16 states each, plus combinational glue, in a single chip. The 10 ns tPD ensures predictable state-to-output timing, and the non-volatile EEPROM configuration means the controller powers up in a known state without external boot memory. Industrial applications include motor controllers, machine-tool sequencers, and protocol converters.
Recommended
Address Decoding and Wait-State Generation
The EPM9560ARI240-10N addresses memory and peripheral decoding with 10 ns propagation delay, ensuring that address-to-chip-select timing remains within ISA, PCI, or proprietary bus budget without wait states. The 560 macrocells can decode wide address ranges - up to 32-bit or beyond - with chip-enable generation for multiple memory banks and peripherals, while internal product-term expansion handles irregular decode patterns cleanly. For wait-state generation, the macrocell flip-flops implement countdown timers that stretch bus cycles. Compared to discrete PAL/GAL decoders, the MAX 9000 device consolidates decode, wait-state logic, and bus control in one reprogrammable chip.
Recommended
Interface Translation Between Logic Families
The EPM9560ARI240-10N bridges 5V TTL, 3.3V LVTTL, and other mixed-voltage logic interfaces because its 5V-tolerant I/Os can drive TTL loads directly while inputs accept 5V signals with proper reference design. The 216 user I/Os enable wide parallel bus translation between legacy 5V peripherals and 3.3V processors, eliminating dozens of bus switches and level translators. Industrial designs use the device to interface between 5V PLC I/O racks and 3.3V controllers. The JTAG ISP also allows the same hardware to be repurposed across multiple interface protocols, reducing SKU proliferation.
Recommended
Industrial Control Systems
The EPM9560ARI240-10N is built for industrial control systems with its -40C to +85C industrial temperature grade and deterministic MAX architecture timing. Process controllers, PLC backplanes, and SCADA interface cards use the device to consolidate sensor multiplexing, encoder decoding, PWM generation, and interlock logic into a single chip. The 12,000 usable gates handle the combinational logic of a small PLC rack, while the 5V I/O drives industrial actuators and relays directly. Non-volatile configuration ensures the controller recovers to a known safe state after power-cycle or brown-out events.
Recommended
Telecommunications Backplane Glue
The EPM9560ARI240-10N serves telecommunications backplane glue applications with 10 ns propagation delay and abundant I/Os for high-density signal routing. Telecom backplanes route clock distribution, frame synchronization, bus arbitration, and alarm monitoring between line cards; the EPM9560ARI240-10N provides deterministic timing for these critical paths, replacing multiple discrete decoders and FIFOs. The 5V supply matches legacy telecom racks, and the industrial temperature range handles outdoor cabinet environments. JTAG boundary scan also simplifies board-test routines for high-density backplanes.
Recommended
Legacy Hardware Maintenance and Last-Time Buy
The EPM9560ARI240-10N is a known-quantity legacy part, and engineers maintaining installed equipment use it for field replacements where the original MAX 9000 architecture is required. Because the device is NRND, replacement boards should be designed with the EPM9560ARC240-10N or a MAX V/MAX II modern equivalent in parallel to mitigate last-time-buy risk. For new designs requiring 5V-tolerant, non-volatile, deterministic logic, this device remains an excellent drop-in solution that exactly replicates legacy board behavior with no firmware rewrite.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560ARI240-10N β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560ARI240-10 | EPM9560ARC240-10N | EPM9560ARC240-10 |
|---|---|---|---|---|
| Brand | Intel | Intel | Intel | Intel |
| Package | RQFP-240 | RQFP-240 - same | RQFP-240 - same | RQFP-240 - same |
| Family | MAX 9000 | MAX 9000 | MAX 9000 | MAX 9000 |
| Macrocells | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 |
| Maximum Internal Frequency | 144.9 MHz | 144.9 MHz | 144.9 MHz | 144.9 MHz |
| Propagation Delay (tPD) | 10 ns (-10 grade) | 10 ns (-10 grade) | 10 ns (-10 grade) | 10 ns (-10 grade) |
| Operating Temperature | -40C to +85C (industrial) | 0C to +70C (commercial) | -40C to +85C (industrial) | 0C to +70C (commercial) |
| Supply Voltage | 5.0V (4.5V-5.5V) | 5.0V (4.5V-5.5V) | 5.0V (4.5V-5.5V) | 5.0V (4.5V-5.5V) |
| In-System Programmability | Yes (5V JTAG ISP) | Yes (5V JTAG ISP) | Yes (5V JTAG ISP) | Yes (5V JTAG ISP) |
Key Differentiators
- Industrial-grade operating temperature range (-40C to +85C) (vs EPM9560ARI240-10)
- 240-RQFP package preserves PCB layout across MAX 9000 family (vs EPM9560ABC356-10)
- 560 macrocells in 240-RQFP - highest density in this footprint (vs EPM9480RC240-20)
Design Notes
Estimated: the EPM9560ARI240-10N draws ICC in the range of 50-200 mA depending on toggle activity; provide a 5.0V regulated supply with at least 10% headroom above the worst-case ICC. Place 0.1 uF decoupling capacitors near every VCC/GND pin pair to suppress simultaneous switching noise. For high-toggle-rate designs, add 10 uF bulk decoupling adjacent to the device to stabilize the rail during large logic transitions.
The RQFP-240 package has a moderate theta_JA (typically 30-40 C/W with standard PCB copper), but at 100+ mA of ICC and 5V supply, internal dissipation can reach 0.5-1W. Estimated junction temperature rise at 1W dissipation is approximately 35 C above ambient. For industrial environments at +85C ambient, ensure adequate PCB copper area or forced airflow to keep junction temperature within the operating range.
Place the EPM9560ARI240-10N on a 4-layer PCB with continuous ground and power planes beneath the device to minimize SSN on the 216 user I/Os. Route all clock inputs on inner layers with controlled impedance (50 ohms single-ended, 100 ohms differential) and keep high-speed outputs short. Provide a star-ground topology at the device's GND pins and avoid splitting the ground plane beneath the RQFP footprint.
Do not assume that any 240-pin RQFP MAX 9000 part is pin-compatible across speed grades without checking the datasheet revision; the -10 grade is the slowest, and the -15 or -20 grades have different propagation delays. The 'N' suffix is critical: omitting it can substitute a commercial-grade part into an industrial design and cause field failures. Always program the device with the latest MAX+PLUS II or Quartus design files matching the silicon revision.
For high-speed interfaces, enable slew-rate limiting on outputs driving long traces, and use series termination (33-68 ohms) on clock and high-speed control outputs to damp reflections. The MAX 9000 supports fast and slow slew-rate options per pin; consult the Quartus/MAX+PLUS II pin-assignment settings to optimize signal integrity versus speed on a per-pin basis.
Compliance Information
Compliance information for EPM9560ARI240-10N was not present in the provided data. AEC-Q100 is not applicable for a 5V legacy industrial CPLD; consult Intel/Altera product environmental compliance documentation for RoHS, REACH, and lead-free status.
