EPM9560GM280-15 vs EPM9560GC280-15N Comparison
Detailed side-by-side comparison of EPM9560GM280-15 by Altera and EPM9560GC280-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560GM280-15 | EPM9560GC280-15N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | NRND | NRND |
| Family | MAX 9000 | — |
| Device Type | EE PLD (EEPROM-based) | — |
| Macrocells | 560 | — |
| Flip-Flops | 772 | — |
| User I/O | 216 | — |
| Logic Array Blocks (LABs) | 35 (16 macrocells each) | — |
| Supply Voltage (Nominal) | 5.0 V | — |
| Supply Voltage (Max) | 5.5 V | — |
| I/O Logic Level Support | 3.3 V or 5 V | — |
| Pin-to-Pin Delay (tPD) | 15 ns (speed grade -15) | — |
| Package | FineLine BGA-280 (GM) | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Process Technology | CMOS EEPROM | — |
| In-System Programmability | Yes (5V ISP via JTAG IEEE 1149.1) | Yes (5.0-V ISP via JTAG) |
| Operating Temperature | -40C to +85C (industrial) | — |
| RoHS Status | ROHS3 Compliant | — |
| MSL Level | 3 (168 Hours) | — |
| Device Family | — | MAX 9000 |
| Product Type | — | EE PLD / CPLD |
| Macrocell Count | — | 560 |
| Usable Gates | — | 12,000 (typical) |
| Propagation Delay (tPD) | — | 16.6 ns |
| Maximum Clock Frequency | — | 117.6 MHz |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Maximum Supply Voltage | — | 5.25 V |
| Logic Technology | — | CMOS EEPROM |
| Boundary-Scan (JTAG) | — | IEEE Std. 1149.1 compliant |
| Package Code | — | PGA / CPGA280 |
| Terminal Form | — | PIN/PEG |
| Operating Temperature Grade | — | Commercial |
| Architecture | — | Multiple Array MatriX (MAX) 3rd generation |