EPM9560GC280-15N - 560-Macrocell MAX 9000 CPLD, CPGA-280 | Intel
MPN: EPM9560GC280-15N ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $168 | $1,680.00 |
| 100 | $152 | $15,200.00 |
| 500 | $138 | $69,000.00 |
| 1,000 | $125 | $125,000.00 |
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View Datasheet →EPM9560GC280-15N Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 |
| Product Type | EE PLD / CPLD |
| Macrocell Count | 560 |
| Usable Gates | 12,000 (typical) |
| Propagation Delay (tPD) | 16.6 ns |
| Maximum Clock Frequency | 117.6 MHz |
| Supply Voltage (VCCINT/VCCIO) | 5.0 V |
| Maximum Supply Voltage | 5.25 V |
| Logic Technology | CMOS EEPROM |
| In-System Programmability | Yes (5.0-V ISP via JTAG) |
| Boundary-Scan (JTAG) | IEEE Std. 1149.1 compliant |
| Package | CPGA-280 (Ceramic Pin Grid Array, 280 pins) |
| Package Code | PGA / CPGA280 |
| Terminal Form | PIN/PEG |
| Operating Temperature Grade | Commercial |
| Architecture | Multiple Array MatriX (MAX) 3rd generation |
EPM9560GC280-15N Pin Configuration
| Pin 1 | I/O — General-purpose I/O pin (LAB bank assignment per datasheet) |
| Pin 2 | I/O — General-purpose I/O pin |
| Pin 3 | I/O — General-purpose I/O pin |
| Pin 4 | GND — Ground |
| Pin 5 | I/O — General-purpose I/O pin |
| Pin 6 | I/O — General-purpose I/O pin |
| Pin 7 | I/O — General-purpose I/O pin |
| Pin 8 | VCC — 5.0-V supply |
| Pin 9 | I/O — General-purpose I/O pin |
| Pin 10 | I/O — General-purpose I/O pin |
| Pin 11 | TDI — JTAG Test Data In |
| Pin 12 | TMS — JTAG Test Mode Select |
| Pin 13 | TCK — JTAG Test Clock |
| Pin 14 | TDO — JTAG Test Data Out |
| Pin 15 | I/O — General-purpose I/O pin |
| Pin 16 | GND — Ground |
| Pin 17 | I/O — General-purpose I/O pin |
| Pin 18 | I/O — General-purpose I/O pin |
| Pin 19 | OE1 — Global Output Enable bank 1 |
| Pin 20 | OE2 — Global Output Enable bank 2 |
| Pin 21 | GCLK1 — Global Clock input 1 |
| Pin 22 | GCLK2 — Global Clock input 2 |
| Pin 23 | I/O — General-purpose I/O pin |
| Pin 24 | VCC — 5.0-V supply |
| Pin 25 | I/O — General-purpose I/O pin |
| Pin 26 | I/O — General-purpose I/O pin |
| Pin 27 | I/O — General-purpose I/O pin |
| Pin 28 | I/O — General-purpose I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560GC280-15N is suitable for 7 applications: High-Density Glue Logic in Telecom Systems, Microprocessor Address Decoding and Bank Switching, Industrial Control and Machine Automation, Bus Interface and Protocol Bridging, State Machine and Sequencer Implementation, Legacy Avionics and Defense Electronics, Prototype and Educational Development Platform.
High-Density Glue Logic in Telecom Systems
The EPM9560GC280-15N serves as high-density glue logic in legacy telecom platforms where deterministic timing and high macrocell count matter most. Its 560 macrocells (12,000 usable gates) easily absorb complex address decoding, bus arbitration, and protocol-bridging functions that would otherwise require multiple discrete PAL/GAL devices. The MAX architecture's fixed interconnect delay — independent of routing — simplifies static timing closure for 117.6 MHz operation in central-office equipment. Designers often pair this CPLD with Altera's MAX+PLUS II toolchain to implement T1/E1 framer interfaces and PBX backplane controllers, where its 280-pin ceramic PGA package supports the through-hole backplane assembly still common in telecom hardware.
Recommended
Microprocessor Address Decoding and Bank Switching
In legacy 5.0-V microprocessor systems, the EPM9560GC280-15N functions as a high-capacity address decoder and bank-selector. Its 560 macrocells easily handle 32-bit address decoding across multiple memory and I/O banks, with predictable propagation delay of 16.6 ns ensuring clean chip-select timing for the CPU read/write cycle. The JTAG ISP interface lets engineers iterate the decode map on assembled PCBs without replacing the device, which is invaluable during debug. The 280-pin CPGA package is well suited to through-hole backplanes of VME, Multibus, and STD-bus systems where the part still ships in production.
Recommended
Industrial Control and Machine Automation
The EPM9560GC280-15N is deployed in industrial control and machine-automation platforms where its 5.0-V tolerance and ceramic PGA package suit long-life through-hole assemblies. The 560 macrocells host combinational and sequential logic for motor controllers, sensor-multiplexer sequencers, and safety-interlock state machines with deterministic 16.6 ns tPD. JTAG boundary-scan per IEEE 1149.1 simplifies board-test fixtures, a key requirement for high-volume manufacturing of PLCs and motion controllers. Industrial designs also benefit from the part's commercial temperature grade and Altera's long-term MAX 9000 support for industrial customers.
Recommended
Bus Interface and Protocol Bridging
Engineers use the EPM9560GC280-15N as a bridge between legacy and modern buses — for example, ISA-to-PCI, VME-to-PCI, or proprietary backplane protocols. Its 12,000 usable gates comfortably implement FIFOs, handshaking logic, and protocol-state machines, while the deterministic timing simplifies verification against bus AC specifications. The JTAG interface enables in-system debugging of complex state machines via Altera's MAX+PLUS II. With 280 ceramic PGA pins, the device also offers ample I/O for parallel-bus applications common in legacy defense and aerospace subsystems.
Recommended
State Machine and Sequencer Implementation
The EPM9560GC280-15N hosts complex state machines, sequencers, and timing controllers used in test equipment, instrumentation, and embedded systems. Its 560 macrocells and 117.6 MHz fMAX support multi-state FSMs with 16.6 ns state-transition latency, while the predictable interconnect delay allows designers to budget timing without re-routing iterations. Engineers commonly implement encoder/decoder sequencers, I2C/SPI controller cores, and timer/counter chains. The EEPROM-based configuration memory ensures that the programmed state machine survives power cycles, ideal for unattended industrial or remote installations.
Recommended
Legacy Avionics and Defense Electronics
The EPM9560GC280-15N remains in service for legacy avionics and defense platforms where its ceramic CPGA package meets long-term reliability and through-hole soldering requirements. With 560 macrocells and JTAG boundary scan, it implements timing-critical logic in radar signal processors, flight-control subsystems, and secure communication equipment. The 5.0-V tolerant I/O matches older ASIC and bus interfaces still prevalent in defense electronics. Note that for new defense designs, designers should validate availability through authorized Altera/Intel distributors and plan migration paths onto modern MAX 10 or Cyclone devices.
Recommended
Prototype and Educational Development Platform
Universities and engineering labs use the EPM9560GC280-15N as a teaching platform for digital design, VHDL/Verilog synthesis, and JTAG-based debugging. Its 560 macrocells offer enough capacity for student projects such as CPU cores, peripheral controllers, and DSP pipelines, while the 280-pin ceramic PGA package fits into standard PLCC/PGA sockets on FPGA/CPLD training boards. Altera's MAX+PLUS II toolchain — though legacy — is widely available and remains the simplest introduction to hardware description languages. The part's deterministic timing also makes it suitable for illustrating synchronous design principles in undergraduate curricula.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560GC280-15N — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560GC280-15 | EPM9560GC280-20 | EPM9320GC280-15 | EPM9320GC280-20 |
|---|---|---|---|---|---|
| Brand | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) | Intel (Altera) |
| Package | CPGA-280 (280-pin Ceramic PGA) | CPGA-280 - same | CPGA-280 - same | CPGA-280 - same | CPGA-280 - same |
| Macrocell Count | 560 | 560 (same) | 560 (same) | 320 (-43%) | 320 (-43%) |
| Propagation Delay (tPD) | 16.6 ns | 16.6 ns (same) | 20.0 ns (slower) | 15.0 ns (faster) | 20.0 ns (slower) |
| Maximum Clock Frequency | 117.6 MHz | 117.6 MHz (same) | 100 MHz (slower) | 125 MHz (faster) | 100 MHz (slower) |
| Usable Gates | 12,000 | 12,000 (same) | 12,000 (same) | 6,000 (-50%) | 6,000 (-50%) |
| Supply Voltage | 5.0 V | 5.0 V (same) | 5.0 V (same) | 5.0 V (same) | 5.0 V (same) |
| JTAG/ISP | Yes (IEEE 1149.1) | Yes (same) | Yes (same) | Yes (same) | Yes (same) |
| Temperature Grade | Commercial (N-suffix) | Commercial (no N-suffix designation) | Commercial | Commercial | Commercial |
Key Differentiators
- Highest macrocell count in MAX 9000 family (vs EPM9320GC280-15)
- Faster timing margin than -20 grade (vs EPM9560GC280-20)
- Commercial-grade N-suffix variant optimized for cost-sensitive designs (vs EPM9560GC280-15 (no N-suffix))
Design Notes
The EPM9560GC280-15N requires a 5.0-V ±5% supply with a maximum rating of 5.25 V. Place a 0.1 µF ceramic decoupling capacitor as close as possible to every VCC pin, and add at least one bulk 10–47 µF tantalum or electrolytic capacitor near the package. The CPGA-280 package typically has 8–12 VCC/GND pairs distributed across the pin grid; failure to decouple all pairs results in logic errors at high clock rates. Verify power sequencing so that VCCIO tracks VCCINT within the datasheet specification to avoid latch-up.
The 280-pin ceramic PGA package requires a through-hole footprint with a PGA socket or pin-in-hole solder joints. Maintain a minimum pad diameter of 1.5 mm with 2.54 mm pitch and via-in-pad stitching for ground returns. Provide at least four PCB layers with a dedicated ground plane beneath the package to control return-path inductance. The ceramic package's CTE mismatch with FR-4 PCBs demands thermal-relief pad geometry — avoid solid thermal ties that stress the ceramic during soldering.
Do not assume the EPM9560GC280-15N is 3.3-V tolerant — its I/O and core both operate at 5.0 V. Driving inputs above 5.25 V or below -0.5 V permanently damages the device. The -N suffix indicates commercial temperature grade (0°C to +70°C); for industrial applications, request the -I suffix variant. Be aware that the -15 speed grade provides 16.6 ns tPD, which may not meet timing at 125 MHz; choose the -10 grade (10 ns tPD) if your design targets higher frequencies.
The MAX 9000 architecture guarantees fixed interconnect delays, but global clock pins (GCLK1, GCLK2) and JTAG pins (TCK, TMS, TDI, TDO) still require careful routing. Keep JTAG traces short (<50 mm) and isolate them from switching I/O lines; add a 10 kΩ pull-up on TCK and TMS per IEEE 1149.1 recommendations. For global clocks, route on a dedicated layer with controlled impedance (50 Ω typical) and avoid stubs. Use Altera's MAX+PLUS II timing analyzer to verify setup/hold margins before sign-off.
Compliance Information
Ceramic PGA packages from the MAX 9000 era (1990s) were not always RoHS compliant; check manufacturer documentation for specific compliance status. AEC-Q100 not applicable — this is a commercial-grade programmable logic device, not an automotive-qualified IC.
