EPM9560GM280-15 - 560 Macrocells MAX 9000 PLD 5V | Altera
MPN: EPM9560GM280-15 ✗ End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $165 | $1,650.00 |
| 100 | $145 | $14,500.00 |
| 500 | $125 | $62,500.00 |
| 1,000 | $110 | $110,000.00 |
Drop-in alternatives for EPM9560GM280-15 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool — Select alternative parts for side-by-side comparison:
EPM9560GC280-15
✅ Drop-In✓ In Stock
$115 / Unit
View Datasheet →EPM9560GI280-15
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View Datasheet →EPM9560GC280-15N
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$125 / Unit
View Datasheet →EPM9560GC280-20
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$360 / Unit
View Datasheet →EPM9560GC280-20N
✅ Drop-In✓ In Stock
$285 / Unit
View Datasheet →EPM9560GI280-20
✅ Drop-In✓ In Stock
$162.5 / Unit
View Datasheet →EPM9560GM280-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | EE PLD (EEPROM-based) |
| Macrocells | 560 |
| Flip-Flops | 772 |
| User I/O | 216 |
| Logic Array Blocks (LABs) | 35 (16 macrocells each) |
| Supply Voltage (Nominal) | 5.0 V |
| Supply Voltage (Max) | 5.5 V |
| I/O Logic Level Support | 3.3 V or 5 V |
| Pin-to-Pin Delay (tPD) | 15 ns (speed grade -15) |
| Package | FineLine BGA-280 (GM) |
| Process Technology | CMOS EEPROM |
| In-System Programmability | Yes (5V ISP via JTAG IEEE 1149.1) |
| Operating Temperature | -40C to +85C (industrial) |
| RoHS Status | ROHS3 Compliant |
| MSL Level | 3 (168 Hours) |
EPM9560GM280-15 fineline bga-280 (gm) Pin Configuration Guide
Complete pinout information for EPM9560GM280-15 (fineline bga-280 (gm) package). This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560GM280-15.
Refer to the datasheet for full pin configuration.
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560GM280-15 is suitable for 6 applications: Telecom Line-Card Glue Logic, Industrial Control & PLC Backplanes, PCI / VME Bus Bridge Implementation, Legacy Avionics & Military Subsystems, High-Density State-Machine Controllers, Prototyping & ASIC Emulation Platform.
Telecom Line-Card Glue Logic
The EPM9560GM280-15 is well-suited to telecom line-card glue logic where 216 user I/Os and 560 macrocells are needed to bridge legacy bus interfaces. Its 15 ns pin-to-pin delay handles T1/E1 framing and HDLC controllers without timing closure issues, while the JTAG-based 5V ISP lets carriers perform field firmware updates on installed cards. The 280-ball FineLine BGA keeps the line-card PCB dense, and MultiVolt I/O lets 5V logic interface to 3.3V framers without external level shifters. Compared with a discrete 74LS glue-logic implementation, the part typically reduces board area by 60-70%.
Recommended
Industrial Control & PLC Backplanes
In PLC backplanes and industrial controllers, the EPM9560GM280-15 provides deterministic state-machine execution at 560 macrocells with EEPROM non-volatile storage, eliminating the boot PROM needed by SRAM-based FPGAs. The 5V ISP via JTAG (IEEE 1149.1) supports in-field firmware upgrades on the factory floor, and the 280-ball BGA offers enough I/O for parallel backplane buses. With operating temperatures from -40C to +85C (industrial), the part handles cabinet environments. Power dissipation at 5V is dominated by I/O toggling; estimate 1.5-2.0W typical for a fully-utilised design (Estimated, based on 216 I/O at 20 MHz toggle).
Recommended
PCI / VME Bus Bridge Implementation
The EPM9560GM280-15 historically implemented PCI and VME bus bridges where 216 I/Os and high macrocell density were needed to combine target/master state machines, parity logic, and address decoding in a single device. The 15 ns tPD comfortably meets 33 MHz PCI timing (30 ns bus cycle). The JTAG ISP allows board-level test access, and the 280-ball BGA keeps the bridge chip compact on multilayer backplanes. For modern designs, consider the MAX V 5M2400ZE64 or a soft IP core in a Cyclone FPGA; the EPM9560GM280-15 remains useful for legacy and long-lifecycle systems.
Recommended
Legacy Avionics & Military Subsystems
Avionics subsystems that were designed around the EPM9560GM280-15 use its 5V supply tolerance, 216 MultiVolt I/Os, and JTAG-based ISP for mission-critical signal routing. The non-volatile EEPROM configuration is particularly valuable - it avoids the configuration-time vulnerability of SRAM-based FPGAs at power-up. While new avionics designs use radiation-hardened FPGAs, thousands of fielded subsystems still rely on the MAX 9000 family, and the GM280 package remains on certified BOMs. For obsolescence management, the GC280 (ceramic) variant is preferred in high-reliability builds.
Recommended
High-Density State-Machine Controllers
For complex multi-state control applications such as disk-channel controllers, tape transports, or instrumentation sequencers, the EPM9560GM280-15 offers 772 flip-flops across 560 macrocells - more than sufficient for 32-bit counters, CRC engines, and FIFOs. The 15 ns tPD allows state transitions at up to 66 MHz internally (Estimated, from tPD ÷ 2), and the 216 I/Os provide plenty of flag/status lines. Designers using MAX+plus II or Quartus can target this device from legacy schematics, and the EEPROM storage means the controller powers up in a known state on every cold start.
Recommended
Prototyping & ASIC Emulation Platform
Before committing to a gate-array ASIC run, design teams used the EPM9560GM280-15 to emulate multi-chip glue logic on a single programmable device. The 560 macrocells cover ~10,000 gates of conventional logic, and the 280-ball BGA exposes nearly every signal to the test bench. ISP via JTAG allows rapid design iteration: recompile, re-program via ByteBlaster, re-test - all without removing the chip from the socket. The 5V I/O tolerance also lets the prototype interface directly with 5V peripherals. For modern prototyping, Cyclone IV or MAX 10 are preferred, but the EPM9560GM280-15 remains in many university and design-lab inventories.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560GM280-15 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560GC280-15 | EPM9560GI280-15 | EPM9560GC280-15N | EPM9560GC280-20 |
|---|---|---|---|---|---|
| Package | FineLine BGA-280 (GM) | PGA-280 (GC) - same die, different footprint | FineLine BGA-280 (GI) - same GM family | PGA-280 (GC) - same die, lead-free | PGA-280 (GC) - same die, 20 ns |
| Brand | Altera (Intel legacy) | Altera (Intel legacy) | Altera (Intel legacy) | Altera (Intel legacy) | Altera (Intel legacy) |
| Macrocells | 560 | 560 | 560 | 560 | 560 |
| Flip-Flops | 772 | 772 | 772 | 772 | 772 |
| User I/O | 216 | 216 | 216 | 216 | 216 |
| Speed Grade (tPD) | 15 ns | 15 ns | 15 ns | 15 ns | 20 ns (+33% slower) |
| Supply Voltage | 5.0 V (5.5 V max) | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| I/O MultiVolt | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V | 3.3 V or 5 V |
| Lead-Free / RoHS | ROHS3 Compliant | ROHS3 Compliant | ROHS3 Compliant | Lead-free (N suffix) - ROHS | ROHS3 Compliant |
| Approx Unit Price (USD, as of 2026-09-13) | 185.00 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Highest macrocell density in the MAX 9000 family (vs EPM9480RC240-15)
- FineLine BGA (GM) with 216 user I/Os (vs EPM9560ARC208-10)
- 5V in-system programmability via JTAG (vs MAX II EPM240T100C5N)
Design Notes
Estimated: at 5.0V VCC with 216 I/O toggling at 20 MHz and 15pF load, the EPM9560GM280-15 draws approximately 1.5-2.0W (based on I/O toggle power ≈ C·V²·f summed across 216 outputs plus core quiescent). Use at least 4 power/ground ball pairs on each BGA quadrant, and stitch 0.1µF + 10µF decoupling across VCC pins. The FineLine BGA die is intolerant of VCC ripple above 50mV; keep switching regulators out of the 1cm plane.
JTAG chain integrity is critical for 5V ISP on the EPM9560GM280-15. Route TCK with a 33Ω series damping resistor at the driver, keep TMS/TDI/TDO traces ≤ 5cm, and place a 10kΩ pull-up on TCK. For multi-device JTAG chains, add 33Ω damping at every TCK tap. Boundary-scan (IEEE 1149.1) coverage is only as good as the chain routing - signal integrity issues here prevent ISP and cause false test failures.
Do not exceed the 5.5V absolute-maximum VCC; transients from a poorly-regulated supply can permanently damage the EEPROM cells. MultiVolt I/O banks must each have their VCCIO tied to either 3.3V or 5V - floating a VCCIO pin causes the bank to back-power through I/O diodes and can latch up the part. Finally, the '-15' suffix is a speed grade, not a temperature grade; check the full ordering code (e.g. EPM9560GM280-15N) for the industrial/commercial temp range.
The 280-ball FineLine BGA exposes a large thermal pad array; for continuous 2W+ dissipation, fan-out the inner balls to a copper plane on top inner-layer with thermal vias on a 1.0mm pitch grid to the opposite side. Without this, junction temperature can exceed 100°C in still air, triggering EEPROM write-cycle degradation. Industrial-grade variants (EPM9560GI280-15) include thermal characterisation data in the MAX 9000 datasheet appendix.
Compliance Information
ROHS3 Compliant per fpgalink.com listing (2026-09-13). Lead-free confirmed; REACH, halogen-free, and conflict-minerals status not stated in verified data - default to unknown. AEC-Q100 not applicable: this is an industrial/commercial PLD, not an automotive-grade IC.
