EPM9560RC208-10 vs EPM9560RC208-13 Comparison

Detailed side-by-side comparison of EPM9560RC208-10 by Intel and EPM9560RC208-13 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC208-10 EPM9560RC208-13
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) —
Macrocells 560 560
Logic Array Blocks (LABs) 16 20
Maximum User I/O Pins 212 (208-pin package variant) —
Usable Gates 12,000 12,000
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Frequency (fMAX) [DATA_NEEDED: internal toggle frequency in MHz] —
Supply Voltage (VCCINT) 5.0 V —
I/O Standards Supported 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) —
Configuration Memory EEPROM (in-system programmable via JTAG) —
Process Technology 0.30 µm CMOS EEPROM —
Operating Temperature 0C to +70C (commercial) —
Package 208-pin RQFP (Plastic Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
Mounting Type Surface Mount Surface Mount
Lead-Free [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] —
RoHS Status [DATA_NEEDED: not stated in retrieved distributor listings] [DATA_NEEDED: RoHS status]
Programmability JTAG (IEEE 1149.1) in-system programming —
Device Family — MAX 9000 EPLD
User I/O Pins — 208
Package Code — RC208
Speed Grade — -13 (13 ns pin-to-pin)
Propagation Delay (tPD) — 13 ns
Maximum Clock Frequency — 125 MHz
Supply Voltage — 5.0 V
Configuration Technology — EEPROM (non-volatile)
Programming Interface — IEEE 1149.1 JTAG
Operating Temperature Range — 0C to +70C (commercial)
Lead-Free Status — [DATA_NEEDED: lead-free status]
MSL Level — [DATA_NEEDED: MSL level]

Datasheets & Resources

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