EPM9560RC208-13 - MAX 9000 CPLD 560 Macrocell | Altera
MPN: EPM9560RC208-13 ✗ End of Life| Qty | Unit Price | Extended |
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| 1 | $0 | $0.00 |
| 10 | $0 | $0.00 |
| 100 | $0 | $0.00 |
| 500 | $0 | $0.00 |
| 1,000 | $0 | $0.00 |
Drop-in alternatives for EPM9560RC208-13 — same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560RC208-12
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View Datasheet →EPM9560RC208-10
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$15.4 / Unit
View Datasheet →EPM9560RC208-10N
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$175 / Unit
View Datasheet →EPM9560RC208-15
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View Datasheet →EPM9560RC208-12C
✅ Drop-In📋 Reference alternative (not in catalog)
EPM9560RC208-13 Maximum Ratings & Electrical Characteristics
| Device Family | MAX 9000 EPLD |
| Macrocells | 560 |
| Usable Gates | 12,000 |
| Logic Array Blocks (LABs) | 20 |
| User I/O Pins | 208 |
| Package | 208-pin RQFP (Power Quad Flat Pack) |
| Package Code | RC208 |
| Speed Grade | -13 (13 ns pin-to-pin) |
| Propagation Delay (tPD) | 13 ns |
| Maximum Clock Frequency | 125 MHz |
| Supply Voltage | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) |
| Programming Interface | IEEE 1149.1 JTAG |
| Operating Temperature Range | 0C to +70C (commercial) |
| Mounting Type | Surface Mount |
EPM9560RC208-13 rc208 Pin Configuration Guide
Complete pinout information for EPM9560RC208-13 (rc208 package) with 208 pins. This digital IC includes GPIO, communication interfaces (UART, SPI, I2C), and power pins. Refer to the manufacturer datasheet for alternate pin functions and configuration options. Essential for embedded system design and PCB layout.
No detailed pinout data available for EPM9560RC208-13.
Refer to the datasheet for full pin configuration.
Estimated pin count: 208 pins (digital package)
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC208-13 is suitable for 6 applications: PCI Bus Glue Logic, Industrial Control State Machines, Telecommunications Line Card Logic, Legacy System Replacement, Memory Controller Glue Logic, Test and Measurement Instrumentation.
PCI Bus Glue Logic
The EPM9560RC208-13 fits PCI bus glue logic because its 208 user I/O pins can directly interface the 32-bit address and data buses without external multiplexing, while the 13 ns pin-to-pin delay and 125 MHz maximum clock frequency satisfy PCI 33 MHz timing margins. The device implements target/slave control, address decoding, and configuration-space registers in a single non-volatile CPLD. Because the MAX 9000 EEPROM configuration is instant-on, the logic is active before the host completes bus enumeration, eliminating the configuration-load delay of SRAM-based FPGAs. A trade-off is the 5.0 V core, which draws more static power than modern 3.3 V CPLDs, so thermal management should be considered in densely packed line cards.
Recommended
Industrial Control State Machines
The EPM9560RC208-13 suits industrial control state machines because its 560 macrocells can implement complex multi-state sequencers with deterministic 13 ns timing, and the non-volatile EEPROM configuration guarantees immediate operation after power-up without a configuration PROM. In factory automation, the device handles interlock logic, encoder decoding, and safety sequencing across 208 I/O lines. The 5.0 V I/O is directly compatible with legacy 5 V sensors and relay drivers, avoiding level shifters. A design consideration is that the commercial 0C to +70C rating limits use in unheated cabinets; industrial-temperature MAX 9000 variants or the MAX 7000 family should be selected for extended-range environments.
Recommended
Telecommunications Line Card Logic
The EPM9560RC208-13 is used in telecommunications line cards for protocol glue logic, timeslot interchange control, and backplane interface management. Its 208 I/O pins accommodate wide TDM buses, and the 125 MHz clock frequency supports high-speed serial framing logic. The EEPROM-based configuration ensures the card is operational immediately on hot insertion, which is critical for carrier-grade uptime. The 13 ns propagation delay provides adequate setup/hold margins for 33 MHz backplane interfaces. Designers should note that the 5.0 V supply requires careful decoupling and that the obsolete lifecycle status means spare inventory planning is essential for long-life telecom equipment.
Recommended
Legacy System Replacement
The EPM9560RC208-13 is a direct replacement for the discontinued 208-pin CQFP version of the EPM9560, as Altera documents the RQFP package as form, fit, and functionally equivalent. This makes it ideal for sustaining legacy systems where the original ceramic package is no longer available. The 560 macrocells and 208 I/O pins preserve the original logic capacity, and the 13 ns timing matches or exceeds the original specification. Engineers replacing CQFP parts must verify the RQFP land pattern and reflow profile, since the package construction differs. The obsolete status of the entire MAX 9000 family means last-time-buy planning is recommended.
Recommended
Memory Controller Glue Logic
The EPM9560RC208-13 implements memory controller glue logic such as DRAM refresh sequencing, chip-select decoding, and wait-state generation. Its 208 I/O pins support wide address and data buses, while the 13 ns propagation delay keeps address decode within a single memory cycle at moderate clock rates. The non-volatile configuration means the controller logic is ready before the CPU releases reset, avoiding boot-time configuration delays. The 5.0 V operation matches legacy memory and bus voltages directly. A key consideration is that the 125 MHz maximum frequency limits use with high-speed DDR interfaces; the device is best suited to SDR and older asynchronous memory subsystems.
Recommended
Test and Measurement Instrumentation
The EPM9560RC208-13 is used in test and measurement instruments for trigger logic, pattern generation, and interface control. The 560 macrocells allow complex trigger state machines, and the 208 I/O pins interface wide parallel buses to acquisition front-ends. The deterministic 13 ns timing ensures repeatable trigger latency, which is essential for measurement accuracy. Non-volatile EEPROM configuration means the instrument is ready instantly at power-on, with no boot delay. The 5.0 V I/O is compatible with legacy instrument backplanes. Designers should account for the commercial temperature range and provide adequate airflow, since the RQFP package dissipates power through the board and leads.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC208-13 — comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-12 | EPM9560RC208-10 | EPM9560RC208-15 |
|---|---|---|---|---|
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Brand | Altera | Altera | Altera | Altera |
| Macrocells | 560 | 560 | 560 | 560 |
| User I/O Pins | 208 | 208 | 208 | 208 |
| Propagation Delay (tPD) | 13 ns | 12 ns | 10 ns | 15 ns |
| Maximum Clock Frequency | 125 MHz | 125 MHz | 125 MHz | 125 MHz |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) | EEPROM (non-volatile) |
| Speed Grade | -13 | -12 | -10 | -15 |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete |
Key Differentiators
- Non-volatile EEPROM configuration (vs EPM9560RC208-12)
- 208 user I/O pins in RQFP (vs EPM9560RC208-10)
- Form, fit, and functional equivalence to CQFP (vs EPM9560RC208-15)
Design Notes
Decouple every VCC pin with a 0.1 uF ceramic capacitor placed as close to the pin as possible, plus at least one 10 uF bulk capacitor per power plane. The MAX 9000 family draws significant transient current during EEPROM programming and high-speed switching; inadequate decoupling causes ground bounce and unreliable JTAG configuration. Estimated: at 5.0 V and 125 MHz operation, dynamic current can exceed 200 mA, so the bulk capacitor should be sized for at least 10x the transient charge.
The 208-pin RQFP package requires a land pattern with 0.50 mm lead pitch. Route all I/O traces with controlled impedance and keep high-speed clock traces away from sensitive analog signals. Provide a solid ground plane under the device and use thermal vias to spread heat, since the RQFP dissipates power through the leads and board. Verify the RQFP land pattern against the Altera package drawing before fabrication, especially when migrating from the discontinued CQFP package.
Do not assume the EPM9560RC208-13 is pin-identical to the CQFP version without checking the package drawing; Altera documents form, fit, and functional equivalence, but the land pattern and reflow profile differ. Also verify the JTAG chain order and TCK/TMS termination, as improper termination causes intermittent programming failures. Because the part is obsolete, always confirm date codes and authenticity from independent distributors before committing to production.
Compliance Information
Compliance data not available in the verified web data. The EPM9560RC208-10N is a lead-free variant; the standard EPM9560RC208-13 lead-free status is unconfirmed. Verify with the manufacturer or distributor before use in regulated markets.
