EPM9560RC208-10 - MAX 9000 CPLD, 560 Macrocells, 208-RQFP | Intel
MPN: EPM9560RC208-10 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $28.5 | $28.50 |
| 10 | $25.2 | $252.00 |
| 100 | $21.8 | $2,180.00 |
| 500 | $18.5 | $9,250.00 |
| 1,000 | $15.4 | $15,400.00 |
Drop-in alternatives for EPM9560RC208-10 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
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EPM9560ARC208-10
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View Datasheet βEPM9560RC/ARC240
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View Datasheet βEPM9480RC208-15
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View Datasheet βEPM9560RC208-10 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 16 |
| Maximum User I/O Pins | 212 (208-pin package variant) |
| Usable Gates | 12,000 |
| Pin-to-Pin Delay (tPD) | 10 ns |
| Supply Voltage (VCCINT) | 5.0 V |
| I/O Standards Supported | 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) |
| Configuration Memory | EEPROM (in-system programmable via JTAG) |
| Process Technology | 0.30 Β΅m CMOS EEPROM |
| Operating Temperature | 0C to +70C (commercial) |
| Package | 208-pin RQFP (Plastic Quad Flat Pack) |
| Mounting Type | Surface Mount |
| Programmability | JTAG (IEEE 1149.1) in-system programming |
EPM9560RC208-10 Pin Configuration
| Pin 1 | I/O β User I/O pin (general purpose, LAB-routed) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | GND β Ground |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | VCC β 5 V supply (core + I/O) |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | TDI β JTAG Test Data In |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | TMS β JTAG Test Mode Select |
| Pin 12 | I/O β User I/O pin |
| Pin 13 | TCK β JTAG Test Clock |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | TDO β JTAG Test Data Out |
| Pin 16 | I/O β User I/O pin |
| Pin 17 | I/O β User I/O pin |
| Pin 18 | GND β Ground |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | I/O β User I/O pin |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | VCC β 5 V supply |
| Pin 23 | I/O β User I/O pin |
| Pin 24 | I/O β User I/O pin |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | I/O β User I/O pin |
| Pin 28 | I/O β User I/O pin |
| Pin 29 | I/O β User I/O pin |
| Pin 30 | GND β Ground |
| Pin 31 | I/O β User I/O pin |
| Pin 32 | I/O β User I/O pin |
| Pin 33 | I/O β User I/O pin |
| Pin 34 | VCC β 5 V supply |
| Pin 35 | I/O β User I/O pin |
| Pin 36 | I/O β User I/O pin |
| Pin 37 | I/O β User I/O pin |
| Pin 38 | I/O β User I/O pin |
| Pin 39 | I/O β User I/O pin |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β User I/O pin |
| Pin 42 | I/O β User I/O pin |
| Pin 43 | I/O β User I/O pin |
| Pin 44 | I/O β User I/O pin |
| Pin 45 | VCC β 5 V supply |
| Pin 46 | I/O β User I/O pin |
| Pin 47 | I/O β User I/O pin |
| Pin 48 | I/O β User I/O pin |
| Pin 49 | I/O β User I/O pin |
| Pin 50 | GND β Ground |
| Pin 51 | I/O β User I/O pin |
| Pin 52 | I/O β User I/O pin |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC208-10 is suitable for 6 applications: Legacy ISA / VME Bus Interface Glue Logic, Industrial Machine Control State Machines, Telecom Line-Card Peripheral Glue Logic, Test & Measurement Instrumentation Front-End, Address Decoding & Chip-Select Generation, Embedded Peripheral Multiplexing & I/O Expansion.
Legacy ISA / VME Bus Interface Glue Logic
The EPM9560RC208-10 is well-suited to legacy ISA-bus and VME-bus interface glue logic where 560 macrocells of deterministic, non-volatile logic decode addresses, latch bus cycles, and arbitrate interrupts. Its 10 ns pin-to-pin delay fits comfortably inside the 25 ns ISA-bus cycle budget, while its EEPROM-based configuration eliminates the cold-start latency and external configuration PROM required by SRAM-based FPGAs. The 208-RQFP package provides up to 212 user I/Os - more than enough for typical 16-bit ISA bus plus chip-select and IRQ expansion. Pair with a 5 V tolerant transceiver (e.g., 74LS245) for a complete bridge solution.
Recommended
Industrial Machine Control State Machines
In industrial machine controllers, the EPM9560RC208-10 implements the deterministic state machines that govern stepper-motor sequencing, conveyor interlocks, and safety cutoffs. The MAX 9000 family's deterministic FastTrack interconnect guarantees identical timing regardless of how the design is routed - critical for safety-rated controllers where a timing race could cause a fault. The 16 LABs and 560 macrocells accommodate large FSMs (20-50 states) plus parallel I/O scan logic. The 5 V I/O tolerance and 0 to +70 C commercial temperature range suit factory-floor enclosures.
Recommended
Telecom Line-Card Peripheral Glue Logic
In telecom line cards the EPM9560RC208-10 performs address decoding, timing generation, and protocol state-machine functions that previously required 5-10 discrete 22V10 / PAL devices. The 560-macrocell capacity and 212-I/O capability allow consolidation of multiple legacy PALs onto one CPLD, reducing PCB area and improving reliability. The multiVolt I/O supports 5.0 V and 3.3 V interfaces, enabling mixed-voltage designs where a 3.3 V microcontroller interfaces with 5 V framer ASICs. The -10 speed grade handles 50 MHz backplane timing with comfortable margin.
Recommended
Test & Measurement Instrumentation Front-End
Test instruments use the EPM9560RC208-10 to implement programmable range switching, autoranging logic, and measurement sequencing. The 10 ns delay is fast enough to gate trigger events in digital oscilloscopes and counters, while the 560 macrocells accommodate complex sequencing FSMs plus parallel I/O control of relays and attenuators. The deterministic timing ensures trigger-to-acquisition latency is predictable, which is critical in time-interval counters. The 208-RQFP package is easy to hand-prototype during bench development.
Recommended
Address Decoding & Chip-Select Generation
The EPM9560RC208-10 is a classic chip-select generator for systems with multiple peripherals on a shared bus. With 560 macrocells it can decode up to ~30 separate chip-select windows with full address-mask flexibility, while its 10 ns propagation delay keeps the decoder comfortably outside the bus-access timing budget. The EEPROM-based configuration means chip-select maps are non-volatile - no boot loader needed. Designers can change the address map on the bench via JTAG and re-program in seconds without removing the part.
Recommended
Embedded Peripheral Multiplexing & I/O Expansion
Embedded systems with insufficient microcontroller I/O pins use the EPM9560RC208-10 to expand GPIOs and implement complex peripheral multiplexing. The 208-RQFP exposes up to 212 user I/Os - more than any 100-pin MCU - and supports 5 V / 3.3 V / 2.5 V mixed-voltage I/O, which makes it ideal as a companion to 3.3 V ARM Cortex-M microcontrollers that need 5 V-tolerant legacy interface pins. The 10 ns delay supports SPI, I2C, and UART baud-rate generation up to ~50 MHz without timing issues.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC208-10 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560ARC208-10 | EPM9560RC208-15 | EPM9560RC208-20 | EPM9480RC208-15 |
|---|---|---|---|---|---|
| Package | 208-RQFP | 208-RQFP (same) | 208-RQFP (same) | 208-RQFP (same) | 208-RQFP (same) |
| Brand | Intel | Intel | Intel | Intel | Intel |
| Pin-to-Pin Delay (tPD) | 10 ns | 10 ns | 15 ns | 20 ns | 15 ns |
| Macrocells | 560 | 560 | 560 | 560 | 480 |
| Logic Array Blocks (LABs) | 16 | 16 | 16 | 16 | 12 |
| Maximum User I/O | 212 | 212 | 212 | 212 | 212 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 10,000 |
| Lead-Free Finish | No (SnPb) | Yes (Pb-free) | No (SnPb) | No (SnPb) | No (SnPb) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete | Obsolete |
| Typical 1000-pc Pricing (USD, as of 2026-09-13) | $15.40 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Fastest speed grade in the MAX 9560 208-RQFP family (vs EPM9560RC208-15)
- Highest macrocell count in the MAX 9000 family (vs EPM9480RC208-15)
- Pin-compatible speed-grade migration path within MAX 9000 family (vs EPM7256SQC208-10)
Design Notes
The MAX 9000 family is in obsolete lifecycle status. New designs in 2026 should not specify EPM9560RC208-10 unless maintaining legacy hardware - Intel/Altera MAX II (EPM570T100C5N) or MAX 10 (10M08SE144C8G) are active-production alternatives with smaller packages and lower power. For new builds, request a Last-Time-Buy quote from authorized distributors before committing the design.
Estimated: typical VCC current draw for EPM9560RC208-10 is approximately 150 mA standby plus 2-3 mA per MHz of switching per I/O pin. At 50 MHz toggle rate with 50% I/O utilization on a 208-RQFP, budget ~400 mA total from a 5 V rail. Use a 100 uF bulk + 10 uF + 0.1 uF ceramic decoupling network near each VCC pin pair (the device has 4-5 VCC/GND pairs).
The 208-RQFP is a fine-pitch (0.5 mm) gull-wing package - PCB layout requires 4-layer stack-up with dedicated ground plane and signal layers above/below. Allocate at least 4 vias per VCC/GND pair, and route JTAG (TMS, TCK, TDI, TDO) as a 4-wire daisy-chain with 10 kohm pull-ups on TMS and TDI. The 'RC' suffix denotes commercial SnPb finish; for RoHS builds use the 'ARC' variant.
MAX 9000 outputs have edge rates of ~3 ns (TTL-strong drive), which can cause reflections on unterminated traces longer than ~50 mm. For high-speed chip-select or clock outputs, add 33 ohm series damping resistors at the CPLD output. The 10 ns tPD budget is conservative for design - actual measured propagation in silicon is typically 7-9 ns at 5 V / 25 C, giving you 1-3 ns of design margin.
Compliance Information
The 'RC' suffix in EPM9560RC208-10 denotes the standard tin-lead (SnPb) finish per Altera's part-number convention - therefore non-RoHS by default. For RoHS-compliant builds use the 'ARC' suffix variant (EPM9560ARC208-10). Other compliance fields not stated in the retrieved distributor listings.
