EPM9560RC208-10 vs EPM9560RC208-14 Comparison

Detailed side-by-side comparison of EPM9560RC208-10 by Intel and EPM9560RC208-14 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC208-10 EPM9560RC208-14
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Obsolete Obsolete
Family MAX 9000 MAX 9000
Device Type CPLD (Complex Programmable Logic Device) CPLD (Complex Programmable Logic Device)
Macrocells 560 560
Logic Array Blocks (LABs) 16 16
Maximum User I/O Pins 212 (208-pin package variant) —
Usable Gates 12,000 12,000
Pin-to-Pin Delay (tPD) 10 ns —
Maximum Frequency (fMAX) [DATA_NEEDED: internal toggle frequency in MHz] —
Supply Voltage (VCCINT) 5.0 V —
I/O Standards Supported 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O) —
Configuration Memory EEPROM (in-system programmable via JTAG) —
Process Technology 0.30 µm CMOS EEPROM 0.35 µm CMOS EEPROM
Operating Temperature 0C to +70C (commercial) —
Package 208-pin RQFP (Plastic Quad Flat Pack) 208-pin RQFP (PQFP)
Mounting Type Surface Mount Surface Mount
Lead-Free [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing] —
RoHS Status [DATA_NEEDED: not stated in retrieved distributor listings] Non-compliant (legacy part)
Programmability JTAG (IEEE 1149.1) in-system programming —
User I/O Pins — 149
Maximum Operating Frequency — 117.6 MHz
Pin-to-Pin Propagation Delay — 14 ns
Supply Voltage — 5 V
I/O Voltage Support — 3.3 V / 5 V
Program Memory Type — EEPROM (non-volatile)
In-System Programmability — Yes (JTAG, IEEE 1149.1)

Datasheets & Resources

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