EPM9560RC208-14 - MAX 9000 CPLD, 12K Gates, 560 Macrocells | Altera
MPN: EPM9560RC208-14 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $48.5 | $48.50 |
| 10 | $42 | $420.00 |
| 100 | $35.75 | $3,575.00 |
| 250 | $31.2 | $7,800.00 |
| 500 | $27.9 | $13,950.00 |
Drop-in alternatives for EPM9560RC208-14 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RC208-13
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View Datasheet βEPM9560RC208-10
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View Datasheet βEPM9560RC208-15
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View Datasheet βEPM9560ARC208-10
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View Datasheet βEPM9560ARC208-10N
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View Datasheet βEPM9560RC208-14 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) |
| Usable Gates | 12,000 |
| Macrocells | 560 |
| Logic Array Blocks (LABs) | 16 |
| User I/O Pins | 149 |
| Maximum Operating Frequency | 117.6 MHz |
| Pin-to-Pin Propagation Delay | 14 ns |
| Supply Voltage | 5 V |
| I/O Voltage Support | 3.3 V / 5 V |
| Program Memory Type | EEPROM (non-volatile) |
| In-System Programmability | Yes (JTAG, IEEE 1149.1) |
| Package | 208-pin RQFP (PQFP) |
| Mounting Type | Surface Mount |
| Process Technology | 0.35 Β΅m CMOS EEPROM |
| RoHS Status | Non-compliant (legacy part) |
EPM9560RC208-14 Pin Configuration
| Pin 1 | I/O β User I/O pin (bank 1) |
| Pin 2 | I/O β User I/O pin (bank 1) |
| Pin 3 | I/O β User I/O pin (bank 1) |
| Pin 4 | I/O β User I/O pin (bank 1) |
| Pin 5 | I/O β User I/O pin (bank 1) |
| Pin 6 | I/O β User I/O pin (bank 1) |
| Pin 7 | I/O β User I/O pin (bank 1) |
| Pin 8 | I/O β User I/O pin (bank 1) |
| Pin 9 | I/O β User I/O pin (bank 1) |
| Pin 10 | I/O β User I/O pin (bank 1) |
| Pin 11 | I/O β User I/O pin (bank 1) |
| Pin 12 | I/O β User I/O pin (bank 1) |
| Pin 13 | GND β Ground |
| Pin 14 | I/O β User I/O pin (bank 2) |
| Pin 15 | I/O β User I/O pin (bank 2) |
| Pin 16 | I/O β User I/O pin (bank 2) |
| Pin 17 | I/O β User I/O pin (bank 2) |
| Pin 18 | I/O β User I/O pin (bank 2) |
| Pin 19 | I/O β User I/O pin (bank 2) |
| Pin 20 | I/O β User I/O pin (bank 2) |
| Pin 21 | I/O β User I/O pin (bank 2) |
| Pin 22 | I/O β User I/O pin (bank 2) |
| Pin 23 | I/O β User I/O pin (bank 2) |
| Pin 24 | I/O β User I/O pin (bank 2) |
| Pin 25 | I/O β User I/O pin (bank 2) |
| Pin 26 | I/O β User I/O pin (bank 2) |
| Pin 27 | GND β Ground |
| Pin 28 | I/O β User I/O pin (bank 3) |
| Pin 29 | I/O β User I/O pin (bank 3) |
| Pin 30 | I/O β User I/O pin (bank 3) |
| Pin 31 | I/O β User I/O pin (bank 3) |
| Pin 32 | I/O β User I/O pin (bank 3) |
| Pin 33 | I/O β User I/O pin (bank 3) |
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| Pin 35 | I/O β User I/O pin (bank 3) |
| Pin 36 | I/O β User I/O pin (bank 3) |
| Pin 37 | I/O β User I/O pin (bank 3) |
| Pin 38 | I/O β User I/O pin (bank 3) |
| Pin 39 | I/O β User I/O pin (bank 3) |
| Pin 40 | GND β Ground |
| Pin 41 | I/O β User I/O pin (bank 4) |
| Pin 42 | I/O β User I/O pin (bank 4) |
| Pin 43 | I/O β User I/O pin (bank 4) |
| Pin 44 | I/O β User I/O pin (bank 4) |
| Pin 45 | I/O β User I/O pin (bank 4) |
| Pin 46 | I/O β User I/O pin (bank 4) |
| Pin 47 | I/O β User I/O pin (bank 4) |
| Pin 48 | I/O β User I/O pin (bank 4) |
| Pin 49 | I/O β User I/O pin (bank 4) |
| Pin 50 | I/O β User I/O pin (bank 4) |
| Pin 51 | I/O β User I/O pin (bank 4) |
| Pin 52 | I/O β User I/O pin (bank 4) |
| Pin 53 | GND β Ground |
| Pin 54 | I/O β User I/O pin (bank 5) |
| Pin 55 | I/O β User I/O pin (bank 5) |
| Pin 56 | I/O β User I/O pin (bank 5) |
| Pin 57 | I/O β User I/O pin (bank 5) |
| Pin 58 | I/O β User I/O pin (bank 5) |
| Pin 59 | I/O β User I/O pin (bank 5) |
| Pin 60 | I/O β User I/O pin (bank 5) |
| Pin 61 | I/O β User I/O pin (bank 5) |
| Pin 62 | I/O β User I/O pin (bank 5) |
| Pin 63 | I/O β User I/O pin (bank 5) |
| Pin 64 | I/O β User I/O pin (bank 5) |
| Pin 65 | I/O β User I/O pin (bank 5) |
| Pin 66 | GND β Ground |
| Pin 67 | I/O β User I/O pin (bank 6) |
| Pin 68 | I/O β User I/O pin (bank 6) |
| Pin 69 | I/O β User I/O pin (bank 6) |
| Pin 70 | I/O β User I/O pin (bank 6) |
| Pin 71 | I/O β User I/O pin (bank 6) |
| Pin 72 | I/O β User I/O pin (bank 6) |
| Pin 73 | I/O β User I/O pin (bank 6) |
| Pin 74 | I/O β User I/O pin (bank 6) |
| Pin 75 | I/O β User I/O pin (bank 6) |
| Pin 76 | I/O β User I/O pin (bank 6) |
| Pin 77 | I/O β User I/O pin (bank 6) |
| Pin 78 | I/O β User I/O pin (bank 6) |
| Pin 79 | GND β Ground |
| Pin 80 | I/O β User I/O pin (bank 7) |
| Pin 81 | I/O β User I/O pin (bank 7) |
| Pin 82 | I/O β User I/O pin (bank 7) |
| Pin 83 | I/O β User I/O pin (bank 7) |
| Pin 84 | I/O β User I/O pin (bank 7) |
| Pin 85 | I/O β User I/O pin (bank 7) |
| Pin 86 | I/O β User I/O pin (bank 7) |
| Pin 87 | I/O β User I/O pin (bank 7) |
| Pin 88 | I/O β User I/O pin (bank 7) |
| Pin 89 | I/O β User I/O pin (bank 7) |
| Pin 90 | I/O β User I/O pin (bank 7) |
| Pin 91 | I/O β User I/O pin (bank 7) |
| Pin 92 | GND β Ground |
| Pin 93 | I/O β User I/O pin (bank 8) |
| Pin 94 | I/O β User I/O pin (bank 8) |
| Pin 95 | I/O β User I/O pin (bank 8) |
| Pin 96 | I/O β User I/O pin (bank 8) |
| Pin 97 | I/O β User I/O pin (bank 8) |
| Pin 98 | I/O β User I/O pin (bank 8) |
| Pin 99 | I/O β User I/O pin (bank 8) |
| Pin 100 | I/O β User I/O pin (bank 8) |
| Pin 101 | I/O β User I/O pin (bank 8) |
| Pin 102 | I/O β User I/O pin (bank 8) |
| Pin 103 | I/O β User I/O pin (bank 8) |
| Pin 104 | I/O β User I/O pin (bank 8) |
| Pin 105 | GND β Ground |
| Pin 106 | I/O β User I/O pin (bank 9) |
| Pin 107 | I/O β User I/O pin (bank 9) |
| Pin 108 | I/O β User I/O pin (bank 9) |
| Pin 109 | I/O β User I/O pin (bank 9) |
| Pin 110 | I/O β User I/O pin (bank 9) |
| Pin 111 | I/O β User I/O pin (bank 9) |
| Pin 112 | I/O β User I/O pin (bank 9) |
| Pin 113 | I/O β User I/O pin (bank 9) |
| Pin 114 | I/O β User I/O pin (bank 9) |
| Pin 115 | I/O β User I/O pin (bank 9) |
| Pin 116 | I/O β User I/O pin (bank 9) |
| Pin 117 | I/O β User I/O pin (bank 9) |
| Pin 118 | GND β Ground |
| Pin 119 | I/O β User I/O pin (bank 10) |
| Pin 120 | I/O β User I/O pin (bank 10) |
| Pin 121 | I/O β User I/O pin (bank 10) |
| Pin 122 | I/O β User I/O pin (bank 10) |
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| Pin 124 | I/O β User I/O pin (bank 10) |
| Pin 125 | I/O β User I/O pin (bank 10) |
| Pin 126 | I/O β User I/O pin (bank 10) |
| Pin 127 | I/O β User I/O pin (bank 10) |
| Pin 128 | I/O β User I/O pin (bank 10) |
| Pin 129 | I/O β User I/O pin (bank 10) |
| Pin 130 | GND β Ground |
| Pin 131 | I/O β User I/O pin (bank 11) |
| Pin 132 | I/O β User I/O pin (bank 11) |
| Pin 133 | I/O β User I/O pin (bank 11) |
| Pin 134 | I/O β User I/O pin (bank 11) |
| Pin 135 | I/O β User I/O pin (bank 11) |
| Pin 136 | I/O β User I/O pin (bank 11) |
| Pin 137 | I/O β User I/O pin (bank 11) |
| Pin 138 | I/O β User I/O pin (bank 11) |
| Pin 139 | I/O β User I/O pin (bank 11) |
| Pin 140 | I/O β User I/O pin (bank 11) |
| Pin 141 | I/O β User I/O pin (bank 11) |
| Pin 142 | GND β Ground |
| Pin 143 | GCLK1 β Global clock input 1 |
| Pin 144 | OE2/GCLK2 β Global clock input 2 / output enable 2 |
| Pin 145 | OE1 β Output enable bank 1 |
| Pin 146 | GND β Ground |
| Pin 147 | I/O β User I/O pin (bank 12) |
| Pin 148 | I/O β User I/O pin (bank 12) |
| Pin 149 | I/O β User I/O pin (bank 12) |
| Pin 150 | I/O β User I/O pin (bank 12) |
| Pin 151 | I/O β User I/O pin (bank 12) |
| Pin 152 | I/O β User I/O pin (bank 12) |
| Pin 153 | I/O β User I/O pin (bank 12) |
| Pin 154 | I/O β User I/O pin (bank 12) |
| Pin 155 | I/O β User I/O pin (bank 12) |
| Pin 156 | I/O β User I/O pin (bank 12) |
| Pin 157 | I/O β User I/O pin (bank 12) |
| Pin 158 | GND β Ground |
| Pin 159 | TDI β JTAG Test Data In |
| Pin 160 | TMS β JTAG Test Mode Select |
| Pin 161 | TCK β JTAG Test Clock |
| Pin 162 | VCC β 5 V core supply |
| Pin 163 | GND β Ground |
| Pin 164 | TDO β JTAG Test Data Out |
| Pin 165 | I/O β User I/O pin (bank 13) |
| Pin 166 | I/O β User I/O pin (bank 13) |
| Pin 167 | I/O β User I/O pin (bank 13) |
| Pin 168 | I/O β User I/O pin (bank 13) |
| Pin 169 | I/O β User I/O pin (bank 13) |
| Pin 170 | I/O β User I/O pin (bank 13) |
| Pin 171 | I/O β User I/O pin (bank 13) |
| Pin 172 | I/O β User I/O pin (bank 13) |
| Pin 173 | I/O β User I/O pin (bank 13) |
| Pin 174 | I/O β User I/O pin (bank 13) |
| Pin 175 | GND β Ground |
| Pin 176 | I/O β User I/O pin (bank 14) |
| Pin 177 | I/O β User I/O pin (bank 14) |
| Pin 178 | I/O β User I/O pin (bank 14) |
| Pin 179 | I/O β User I/O pin (bank 14) |
| Pin 180 | I/O β User I/O pin (bank 14) |
| Pin 181 | I/O β User I/O pin (bank 14) |
| Pin 182 | I/O β User I/O pin (bank 14) |
| Pin 183 | I/O β User I/O pin (bank 14) |
| Pin 184 | I/O β User I/O pin (bank 14) |
| Pin 185 | I/O β User I/O pin (bank 14) |
| Pin 186 | I/O β User I/O pin (bank 14) |
| Pin 187 | GND β Ground |
| Pin 188 | I/O β User I/O pin (bank 15) |
| Pin 189 | I/O β User I/O pin (bank 15) |
| Pin 190 | I/O β User I/O pin (bank 15) |
| Pin 191 | I/O β User I/O pin (bank 15) |
| Pin 192 | I/O β User I/O pin (bank 15) |
| Pin 193 | I/O β User I/O pin (bank 15) |
| Pin 194 | I/O β User I/O pin (bank 15) |
| Pin 195 | I/O β User I/O pin (bank 15) |
| Pin 196 | I/O β User I/O pin (bank 15) |
| Pin 197 | I/O β User I/O pin (bank 15) |
| Pin 198 | I/O β User I/O pin (bank 15) |
| Pin 199 | GND β Ground |
| Pin 200 | I/O β User I/O pin (bank 16) |
| Pin 201 | I/O β User I/O pin (bank 16) |
| Pin 202 | I/O β User I/O pin (bank 16) |
| Pin 203 | I/O β User I/O pin (bank 16) |
| Pin 204 | I/O β User I/O pin (bank 16) |
| Pin 205 | I/O β User I/O pin (bank 16) |
| Pin 206 | I/O β User I/O pin (bank 16) |
| Pin 207 | I/O β User I/O pin (bank 16) |
| Pin 208 | I/O β User I/O pin (bank 16) |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC208-14 is suitable for 6 applications: High-Density Glue Logic in Telecommunications, ASIC Prototyping and Logic Emulation, Bus Interface and Address Decoding, Industrial Control and Automation, Legacy Peripheral Bridge and Bus Converter, Test and Measurement Instrument Logic.
High-Density Glue Logic in Telecommunications
The EPM9560RC208-14's 560 macrocells, 149 user I/O pins, and 14 ns pin-to-pin delay make it well suited to telecom line-card glue logic where dozens of small PAL/GAL functions are consolidated onto a single non-volatile device. The 5 V core with mixed 3.3 V/5 V I/O allows direct interfacing to legacy 5 V bus transceivers and modern 3.3 V ASICs without external level shifters. The JTAG (IEEE 1149.1) in-system programmability enables field updates without removing the board, while EEPROM non-volatility guarantees instant-on operation on power-up - critical for telecom systems requiring deterministic cold-start timing. Designers can replace 10-20 discrete 22V10/PALCE610-style devices with one EPM9560, simplifying the BOM and improving testability.
Recommended
ASIC Prototyping and Logic Emulation
With 12,000 usable gates and 560 macrocells, the EPM9560RC208-14 provides enough capacity to prototype ASICs in the 5K-10K gate range across multiple packages on a single PCB. The 14 ns pin-to-pin delay offers accurate emulation of typical ASIC cell delays, while the deterministic timing model (unlike FPGA look-up-table delays) lets engineers validate timing closure before committing to silicon. The JTAG interface enables fast design iterations: a new netlist can be programmed in seconds via BitBlaster or JTAG cable, dramatically shortening prototype turnaround. The 208-pin RQFP package exposes enough I/O to wire the CPLD into the target board's address, data, and control buses during prototyping. Multiple EPM9560 devices can be cascaded through the JTAG chain for multi-chip prototyping flows.
Recommended
Bus Interface and Address Decoding
The EPM9560RC208-14's wide I/O count (149 pins) and 14 ns propagation delay make it ideal for multi-bus address decoding, chip-select generation, and interrupt arbitration in PCI, VME, ISA, and proprietary backplane designs. Its deterministic pin-to-pin delay simplifies worst-case timing analysis for setup/hold margins on synchronous buses, while the 5 V/3.3 V mixed I/O allows direct drive of 5 V peripherals alongside 3.3 V host processors. The EEPROM-backed configuration boots instantly at power-on, eliminating the boot PROM typically required by SRAM-based FPGAs. Designers commonly use the EPM9560 to consolidate scattered 22V10 / 16V8 / 20V8 glue-logic devices into a single part, freeing PCB area and reducing the BOM count on legacy backplane cards.
Recommended
Industrial Control and Automation
The EPM9560RC208-14's 5 V tolerance, robust EEPROM non-volatile configuration, and industrial temperature variants make it well suited for PLCs, motor controllers, and factory-automation controllers where field reliability matters more than cutting-edge speed. Its 560 macrocells can implement complex state machines for sequencing I/O, encoder counters, and safety interlocks in a single chip, while the JTAG port supports field diagnostics and in-system firmware updates without removing the controller from the line. The RQFP-208 package's through-hole-friendly footprint (hand-solderable leads) supports low-volume industrial production runs. The part's deterministic timing also benefits IEC 61131-style PLC scan-cycle scheduling where predictable logic execution is required.
Recommended
Legacy Peripheral Bridge and Bus Converter
Designers bridging legacy peripherals (ISA, VME, PC/104) to modern processors commonly use the EPM9560RC208-14 as a bus-format translator: its 149 I/O pins and 560 macrocells can implement both bus-side state machines simultaneously, while the 14 ns delay is fast enough to keep up with 33 MHz ISA bus cycles. The 5 V I/O tolerance allows direct connection to legacy 5 V peripherals without buffering, and the JTAG port enables late-stage firmware fixes during the bring-up phase. EEPROM configuration eliminates the boot PROM that would otherwise complicate the bridge card's BOM. The 208-pin RQFP package provides enough margin to expose dedicated diagnostic LEDs and test points on the bridge card.
Recommended
Test and Measurement Instrument Logic
The EPM9560RC208-14's non-volatile instant-on behavior, mixed-voltage I/O, and deterministic timing suit bench-top and rack-mount test instruments such as logic analyzers, protocol analyzers, and switch-matrix controllers. The 560 macrocells can implement parallel stimulus generators, protocol-state machines, and trigger sequencers in a single chip, while the JTAG boundary-scan chain simplifies board-level interconnect testing during manufacturing. The 5 V I/O banks tolerate direct connection to legacy 5 V measurement front-ends, and the 14 ns delay supports timing generation at frequencies up to ~70 MHz in real-world designs. The part's long-term availability through independent brokers keeps legacy instruments serviceable decades after their original production run.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC208-14 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC208-13 | EPM9560RC208-12 | EPM9560RC208-10 | EPM9560RC208-15 | EPM9560ARC208-10 | EPM9560ARC208-10N |
|---|---|---|---|---|---|---|---|
| Brand | Altera | Altera | Altera | Altera | Altera | Altera | Altera |
| Package | 208-pin RQFP | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same | 208-pin RQFP - same |
| Pin-to-Pin Delay | 14 ns | 13 ns (-7%) | 12 ns (-14%) | 10 ns (-29%) | 15 ns (+7%) | 10 ns (-29%) | 10 ns (-29%) |
| Macrocells | 560 | 560 | 560 | 560 | 560 | 560 | 560 |
| Usable Gates | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 | 12,000 |
| User I/O Pins | 149 | 149 | 149 | 149 | 149 | 149 | 149 |
| Maximum Frequency | 117.6 MHz | 125 MHz | 135 MHz | 148 MHz | 111 MHz | 148 MHz | 148 MHz |
| Operating Temperature Grade | Commercial (0C to +70C) | Commercial | Commercial | Commercial | Commercial | Industrial/Military | Industrial/Military, lead-free |
Key Differentiators
- Highest non-military speed grade in RQFP-208 package (vs EPM9560RC208-15)
- Commercial temperature grade with full JTAG ISP support (vs EPM9560ARC208-10)
- Standard JTAG boundary-scan for in-system programming (vs EPM7256SQC208-10)
Design Notes
The EPM9560RC208-14 requires a stable 5 V Β±5% supply on VCCINT (pin 162 and additional VCC pins). Place 0.1 Β΅F ceramic decoupling capacitors adjacent to every VCC/GND pair on the package perimeter (every 3-5 pins). Add a bulk 10-47 Β΅F tantalum or aluminum electrolytic capacitor at the board's power entry to suppress switching transients from upstream regulators. The I/O banks can be powered at 3.3 V independently of the 5 V core, allowing mixed-voltage interfacing without external level shifters - verify bank voltage compatibility in the MAX 9000 datasheet before mixing 5 V and 3.3 V peripherals.
The EPM9560 uses Altera's MAX+PLUS II (legacy) or Quartus Prime (newer) design flow - confirm tool version compatibility for the -14 speed grade before starting the design. JTAG programming requires the four dedicated pins (TCK, TMS, TDI, TDO at pins 159-164) to be accessible on the PCB for in-system programming; do not tie any of these pins to ground or VCC. The 208-pin RQFP package has gull-wing leads with 0.5 mm pitch - hand-soldering is feasible but reflow is preferred for production. EEPROM programming cycles are limited (~100 erase/program cycles); design firmware-update flows to minimize unnecessary reprogramming.
Route JTAG signals (TCK, TMS, TDI, TDO) as a short daisy-chain with proper pull-ups on TCK/TMS as required by IEEE 1149.1. Keep global clock pins (GCLK1 at pin 143, GCLK2 at pin 144) routed with controlled impedance and short trace lengths to maintain signal integrity across the 5 V core. For mixed-voltage designs, group 3.3 V I/O into one bank and 5 V I/O into another bank to simplify power routing. Place the EPM9560 close to the devices it interfaces with (memory, ASICs, microprocessors) to minimize propagation delay in critical timing paths.
Compliance Information
Legacy part from Altera (now Intel). Not RoHS-compliant per original manufacturing - lead-free variants available as EPM9560RC208-10N suffix parts. AEC-Q100 not qualified; for automotive applications consider the EPM9560ARI240-10 industrial variant.
