EPM9560RC208-10N vs EPM9560ARC208-10 Comparison

Detailed side-by-side comparison of EPM9560RC208-10N by Intel and EPM9560ARC208-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM9560RC208-10N EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N ⚠ Last Time Buy

Specification Comparison

Parameter EPM9560RC208-10N EPM9560ARC208-10
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy Obsolete
Family MAX 9000 —
Device EPM9560 —
Macro Cells 560 —
Usable Gates 12,000 12,000 gates
Logic Array Blocks (LABs) 16 —
User I/O Pins 153 153 I/O
Pin-to-Pin Delay (tPD1) 10 ns —
Supply Voltage (VCCINT) 5.0 V —
I/O Bank Voltage (VCCIO) 5.0 V —
Package 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (PowerQuad Flat Pack) with exposed pad
Mounting Type Surface Mount Surface Mount
Process Technology CMOS EEPROM —
Programmability In-system via IEEE 1149.1 JTAG —
Operating Temperature [DATA_NEEDED: operating temperature grade] 0 C to +70 C (commercial)
RoHS Status [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Family — MAX 9000A (Multiple Array MatriX)
Programmable Logic Type — CPLD (Complex Programmable Logic Device)
Macrocells — 560 macrocells
Logic Array Blocks — 35 LABs
Propagation Delay (tPD) — 10 ns (speed grade -10)
Internal Frequency — 144.9 MHz
Supply Voltage — 5.0 V
Logic Family — CMOS
Configuration Technology — EEPROM (non-volatile, in-system programmable)
JTAG Interface — IEEE 1149.1 boundary-scan (ISP)
Pin Count — 208 pins

Datasheets & Resources

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