EPM9560RC208-10N vs EPM9560ARC208-10 Ikinahambing

Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC208-10N sa pamamagitan ng Intel at EPM9560ARC208-10 sa pamamagitan ng Intel. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.

Intel
EPM9560RC208-10N EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N - MAX 9000 CPLD 560 Macro 10ns 208-RQFP | Intel

EPM9560RC208-10N ⚠ Huling Pagbili

Pagsanggunian na paghahambing

Parametro EPM9560RC208-10N EPM9560ARC208-10
Brand Intel Intel
Kategorya FPGA & CPLD FPGA & CPLD
Katayuan ng Lifecycle Huling Pagbili Obsolete
Family MAX 9000 —
Device EPM9560 —
Macro Cells 560 —
Usable Gates 12,000 12,000 gates
Logic Array Blocks (LABs) 16 —
User I/O Pins 153 153 I/O
Pin-to-Pin Delay (tPD1) 10 ns —
Supply Voltage (VCCINT) 5.0 V —
I/O Bank Voltage (VCCIO) 5.0 V —
Packhaging 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (PowerQuad Flat Pack) with exposed pad
Uri ng Pagpapasok Surface Mount Surface Mount
Process Technology CMOS EEPROM —
Programmability In-system via IEEE 1149.1 JTAG —
Temperature na Operasyon [DATA_NEEDED: operating temperature grade] 0 C to +70 C (commercial)
Tindminan RoHS [DATA_NEEDED: RoHS status] [DATA_NEEDED: RoHS status]
Device Family — MAX 9000A (Multiple Array MatriX)
Programmable Logic Type — CPLD (Complex Programmable Logic Device)
Macrocells — 560 macrocells
Logic Array Blocks — 35 LABs
Propagation Delay (tPD) — 10 ns (speed grade -10)
Internal Frequency — 144.9 MHz
Volte ng Pagbibigay — 5.0 V
Logic Family — CMOS
Configuration Technology — EEPROM (non-volatile, in-system programmable)
JTAG Interface — IEEE 1149.1 boundary-scan (ISP)
Bilang ng Pin — 208 pins

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