EPM9560RC208-15N vs EPM9560RC208-20C Comparison

Detailed side-by-side comparison of EPM9560RC208-15N by Intel and EPM9560RC208-20C by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Intel
EPM9560RC208-15N EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP

EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP

EPM9560RC208-15N ⚠ Last Time Buy

Specification Comparison

Parameter EPM9560RC208-15N EPM9560RC208-20C
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy Obsolete
Series MAX 9000 —
Device Type CPLD (Complex Programmable Logic Device) EEPROM-based CPLD (EE PLD)
Macrocells 560 560
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 16 —
User I/O 212 (in 208-RQFP, see family datasheet) —
Pin-to-Pin Delay (tPD) 15 ns —
Maximum Internal Frequency 117.6 MHz —
Supply Voltage (VCCINT) 5.0 V —
Programmability In-system via IEEE 1149.1 JTAG —
Configuration Memory CMOS EEPROM (non-volatile) EEPROM (non-volatile)
Package 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
Operating Temperature (commercial) 0C to +70C —
Mounting Type Surface Mount Surface Mount
RoHS Status [DATA_NEEDED: check part marking suffix for lead-free/RoHS] [DATA_NEEDED: RoHS status]
Speed Grade -15 (15 ns tPD) —
Architecture Multiple Array MatriX (MAX) - third generation —
Family — MAX 9000
Flip-Flops — 772
Configurable I/O Lines — 149
Propagation Delay (tPD) — 20 ns (speed grade -20)
Maximum Frequency — 100 MHz
Supply Voltage — 5.0 V
I/O Voltage Support — 3.3 V or 5 V
In-System Programmability — Yes, via IEEE Std. 1149.1 JTAG
JESD-30 Package Code — S-PQFP-G208
Terminal Form — Gull Wing
Operating Temperature Grade — Commercial (0C to +70C)
Technology — CMOS

Datasheets & Resources

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