EPM9560RC208-20C vs EPM9560RC208-15N Comparison
Detailed side-by-side comparison of EPM9560RC208-20C by Altera and EPM9560RC208-15N by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP
EPM9560RC208-15N β Last Time BuySpecification Comparison
| Parameter | EPM9560RC208-20C | EPM9560RC208-15N |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Last_time_buy |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $0.00 | $19.85 |
| Family | MAX 9000 | β |
| Device Type | EEPROM-based CPLD (EE PLD) | CPLD (Complex Programmable Logic Device) |
| Macrocells | 560 | 560 |
| Usable Gates | 12,000 | 12,000 |
| Flip-Flops | 772 | β |
| Configurable I/O Lines | 149 | β |
| Propagation Delay (tPD) | 20 ns (speed grade -20) | β |
| Maximum Frequency | 100 MHz | β |
| Supply Voltage | 5.0 V | β |
| I/O Voltage Support | 3.3 V or 5 V | β |
| Configuration Memory | EEPROM (non-volatile) | CMOS EEPROM (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | β |
| Package | 208-pin RQFP (Power Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| JESD-30 Package Code | S-PQFP-G208 | β |
| Terminal Form | Gull Wing | β |
| Operating Temperature Grade | Commercial (0C to +70C) | β |
| Technology | CMOS | β |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS status] | [DATA_NEEDED: check part marking suffix for lead-free/RoHS] |
| Series | β | MAX 9000 |
| Logic Array Blocks (LABs) | β | 16 |
| User I/O | β | 212 (in 208-RQFP, see family datasheet) |
| Pin-to-Pin Delay (tPD) | β | 15 ns |
| Maximum Internal Frequency | β | 117.6 MHz |
| Supply Voltage (VCCINT) | β | 5.0 V |
| Programmability | β | In-system via IEEE 1149.1 JTAG |
| Operating Temperature (commercial) | β | 0C to +70C |
| Speed Grade | β | -15 (15 ns tPD) |
| Architecture | β | Multiple Array MatriX (MAX) - third generation |