EPM9560RC208-20C vs EPM9560RC208-15N 对比

详细并排对比 EPM9560RC208-20C 出自 Altera 和 EPM9560RC208-15N 出自 Intel。对比关键规格、电气参数、封装、生命周期状态、价格和供货情况,以确定最适合您设计需求的元器件。

Intel
EPM9560RC208-15N EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP

EPM9560RC208-15N - 560-Macrocell MAX 9000 CPLD, 15ns, 208-RQFP

EPM9560RC208-15N ⚠ 最后一次采购

规格对比

参数 EPM9560RC208-20C EPM9560RC208-15N
品牌 Altera Intel
分类 FPGA & CPLD FPGA & CPLD
生命周期状态 Obsolete 最后采购期
库存状态 有库存 有库存
单价(USD) $0.00 $19.85
Family MAX 9000 —
Device Type EEPROM-based CPLD (EE PLD) CPLD (Complex Programmable Logic Device)
Macrocells 560 560
Usable Gates 12,000 12,000
Flip-Flops 772 —
Configurable I/O Lines 149 —
Propagation Delay (tPD) 20 ns (speed grade -20) —
Maximum Frequency 100 MHz —
电源电压 5.0 V —
I/O Voltage Support 3.3 V or 5 V —
Configuration Memory EEPROM (non-volatile) CMOS EEPROM (non-volatile)
In-System Programmability Yes, via IEEE Std. 1149.1 JTAG —
封装 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (Power Quad Flat Pack)
JESD-30 Package Code S-PQFP-G208 —
Terminal Form Gull Wing —
Operating Temperature Grade Commercial (0C to +70C) —
Technology CMOS —
安装类型 Surface Mount Surface Mount
RoHS 状态 [DATA_NEEDED: RoHS status] [DATA_NEEDED: check part marking suffix for lead-free/RoHS]
Series — MAX 9000
Logic Array Blocks (LABs) — 16
User I/O — 212 (in 208-RQFP, see family datasheet)
Pin-to-Pin Delay (tPD) — 15 ns
Maximum Internal Frequency — 117.6 MHz
Supply Voltage (VCCINT) — 5.0 V
Programmability — In-system via IEEE 1149.1 JTAG
Operating Temperature (commercial) — 0C to +70C
Speed Grade — -15 (15 ns tPD)
Architecture — Multiple Array MatriX (MAX) - third generation

数据手册与资源

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