EPM9560RC208-20N vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560RC208-20N by Intel and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-20N | EPM9560RC208-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Device Family | MAX 9000 (EPM9560) | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| Propagation Delay (tPD) | 20 ns | — |
| Package | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| User I/O Pins | 149 | — |
| Supply Voltage | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | IEEE Std. 1149.1 | — |
| Mounting Type | Surface Mount | Surface Mount |
| Operating Temperature | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| RoHS Status | Lead-free (N suffix) | [DATA_NEEDED: RoHS status] |
| Logic Architecture | Multiple Array MatriX (MAX), third-generation CMOS EEPROM | — |
| Flip-Flops | 772 (per EPM9560 series data) | — |
| Speed Grade | -20 (20 ns) | -15 (15 ns pin-to-pin) |
| MSL Level | [DATA_NEEDED: MSL level] | — |
| Family | — | MAX 9000 |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |