EPM9560RC208-20N vs EPM9560RC208-15 比較
詳細並排比較 EPM9560RC208-20N 由 Intel 與 EPM9560RC208-15 由 Altera. 比較關鍵規格、電氣參數、封裝、生命週期狀態、價格與供貨情況，以找出最符合您設計需求的元件。
規格比較
| 參數 | EPM9560RC208-20N | EPM9560RC208-15 |
|---|---|---|
| 品牌 | Intel | Altera |
| 類別 | FPGA & CPLD | FPGA & CPLD |
| 生命週期狀態 | Obsolete | Obsolete |
| Device Family | MAX 9000 (EPM9560) | — |
| Macrocells | 560 | — |
| Usable Gates | 12,000 | 12,000 gates |
| Propagation Delay (tPD) | 20 ns | — |
| 封裝 | 208-pin RQFP (PowerQuad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| User I/O Pins | 149 | — |
| 供應電壓 | 5.0 V | 5.0 V |
| Configuration Technology | EEPROM (non-volatile) | EEPROM (non-volatile) |
| In-System Programmability | Yes, via IEEE Std. 1149.1 JTAG | Yes, via IEEE Std. 1149.1 JTAG |
| JTAG Interface | IEEE Std. 1149.1 | — |
| 安裝類型 | Surface Mount | Surface Mount |
| 工作溫度 | [DATA_NEEDED: operating temperature range] | [DATA_NEEDED: operating temperature range] |
| RoHS 狀態 | Lead-free (N suffix) | [DATA_NEEDED: RoHS status] |
| Logic Architecture | Multiple Array MatriX (MAX), third-generation CMOS EEPROM | — |
| Flip-Flops | 772 (per EPM9560 series data) | — |
| Speed Grade | -20 (20 ns) | -15 (15 ns pin-to-pin) |
| MSL 等級 | [DATA_NEEDED: MSL level] | — |
| Family | — | MAX 9000 |
| Device Type | — | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | — | 560 macro cells |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |