EPM9560RC208-21 vs EPM9560RC208-10 Comparison

Detailed side-by-side comparison of EPM9560RC208-21 by Intel and EPM9560RC208-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC208-21 EPM9560RC208-10
Brand Intel Intel
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy Obsolete
Family MAX 9000 MAX 9000
Architecture Multiple Array MatriX (MAX), third-generation —
Technology CMOS EEPROM-based —
Macrocells 560 560
Usable Gates 12,000 12,000
Logic Array Blocks (LABs) 16 16
Flip-Flops 772 —
Maximum User I/O 149 —
Propagation Delay (speed grade -21) 21 ns (max, per speed grade designation) —
Supply Voltage 5.0 V —
I/O Voltage Tolerance 3.3 V or 5 V (per variant) —
In-System Programmability Yes (IEEE Std. 1149.1 JTAG) —
Package 208-pin RQFP (Power Quad Flat Pack) 208-pin RQFP (Plastic Quad Flat Pack)
Operating Temperature [DATA_NEEDED: industrial or commercial grade -21 suffix] 0C to +70C (commercial)
Configuration Memory EEPROM (non-volatile) EEPROM (in-system programmable via JTAG)
Security Bit Yes (programmable) —
RoHS Status [DATA_NEEDED: confirm RoHS compliance for -21 variant] [DATA_NEEDED: not stated in retrieved distributor listings]
Device Type — CPLD (Complex Programmable Logic Device)
Maximum User I/O Pins — 212 (208-pin package variant)
Pin-to-Pin Delay (tPD) — 10 ns
Maximum Frequency (fMAX) — [DATA_NEEDED: internal toggle frequency in MHz]
Supply Voltage (VCCINT) — 5.0 V
I/O Standards Supported — 5.0 V TTL, 3.3 V LVTTL, 2.5 V (multiVolt I/O)
Process Technology — 0.30 µm CMOS EEPROM
Mounting Type — Surface Mount
Lead-Free — [DATA_NEEDED: confirm lead-free status -10 suffix is conventional Pb-containing]
Programmability — JTAG (IEEE 1149.1) in-system programming

Datasheets & Resources

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