EPM9560RC208-5 vs EPM9560RC208-15 Comparison
Detailed side-by-side comparison of EPM9560RC208-5 by Altera and EPM9560RC208-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC208-5 | EPM9560RC208-15 |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Device Type | CPLD (Complex Programmable Logic Device) | EEPROM-based Complex Programmable Logic Device (CPLD) |
| Macro Cells | 560 | 560 macro cells |
| Usable Gates | 12,000 | 12,000 gates |
| Logic Array Blocks (LABs) | 16 | — |
| Maximum User I/O | 149 | — |
| Dedicated Inputs | 16 | — |
| Flip-Flops | 772 | — |
| Propagation Delay (tPD) | 5 ns | — |
| Internal Counter Frequency (fCNT) | 117.6 MHz | — |
| Supply Voltage (VCC) | 5.0 V | — |
| Package | 208-pin RQFP (Plastic Quad Flat Pack) | 208-pin RQFP (Power Quad Flat Pack) |
| Process Technology | CMOS EEPROM | — |
| Programming Interface | JTAG (IEEE Std 1149.1) + 5V ISP | — |
| Operating Temperature | 0C to +70C (commercial) | [DATA_NEEDED: operating temperature range] |
| RoHS Status | Non-compliant (5V process, legacy RQFP) | [DATA_NEEDED: RoHS status] |
| Pin-to-Pin Delay | — | 15 ns |
| Counter Speed | — | 117.6 MHz |
| Supply Voltage | — | 5.0 V |
| Configuration Technology | — | EEPROM (non-volatile) |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Mounting Type | — | Surface Mount |
| Number of I/O Pins | — | [DATA_NEEDED: number of I/O pins] |
| Logic Array Blocks | — | [DATA_NEEDED: number of logic array blocks] |
| Speed Grade | — | -15 (15 ns pin-to-pin) |
| Architecture | — | Third-generation Multiple Array MatriX (MAX) |