EPM9560RC240-10N vs EPM9560RC240-15N Comparison

Detailed side-by-side comparison of EPM9560RC240-10N by Intel and EPM9560RC240-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.

Specification Comparison

Parameter EPM9560RC240-10N EPM9560RC240-15N
Brand Intel Altera
Category FPGA & CPLD FPGA & CPLD
Lifecycle Status Last Time Buy NRND
Family MAX 9000 MAX 9000 (third-generation Multiple Array MatriX)
Architecture Multiple Array MatriX (MAX) - 3rd generation —
Usable Gates 12,000 12,000
Macrocells 560 560
Logic Array Blocks (LABs) 16 35
User I/Os 212 —
Internal Operating Frequency 144.9 MHz —
Pin-to-Pin Propagation Delay (tPD) 10 ns (-10 speed grade) 15 ns
Supply Voltage 5.0 V 5.0 V
Process Technology 0.65 µm CMOS EEPROM —
Package 240-pin RQFP (Plastic Quad Flat Pack) RQFP-240 (240-pin Plastic Quad Flat Pack)
Programming Interface JTAG (IEEE 1149.1) - in-system programmable —
I/O Standards Supported 5.0 V TTL/CMOS, 3.3 V PCI-compatible —
Operating Temperature (Commercial) 0 °C to +70 °C —
Lead-Free Finish (N suffix) Yes (Pb-free) —
RoHS Status ROHS3 Compliant (per fpgalink.com listing) [DATA_NEEDED: RoHS compliance - older Altera RQFP part]
Moisture Sensitivity Level (MSL) 3 (168 hours) —
Series — MAX 9000
Maximum User I/O Pins — 216
Internal Counter Frequency (fCNT) — 145 MHz
Global Setup Time (tFSU) — [DATA_NEEDED: tFSU for -15 grade]
Clock-to-Output Time (tFCO) — [DATA_NEEDED: tFCO for -15 grade]
Logic Family — CMOS (EEPROM-based)
Programmability — In-system programmable (IEEE 1532/JTAG)
Boundary-Scan Test — JTAG (IEEE 1149.1)
Operating Temperature — 0C to +70C (Commercial)
Mounting Type — Surface Mount

Datasheets & Resources

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