EPM9560RC240-10N vs EPM9560RC240-15N Comparación
Comparación detallada lado a lado de EPM9560RC240-10N por Intel y EPM9560RC240-15N por Altera. Compare las especificaciones clave, los parámetros eléctricos, el encapsulado, el estado del ciclo de vida, los precios y la disponibilidad para determinar el mejor componente para los requisitos de su diseño.
Intel
EPM9560RC240-10N - MAX 9000 CPLD 560 Macrocells 5V 240-Pin RQFP | Intel
EPM9560RC240-10N ⚠ Última compraComparación de especificaciones
| Parámetro | EPM9560RC240-10N | EPM9560RC240-15N |
|---|---|---|
| Marca | Intel | Altera |
| Categoría | FPGA & CPLD | FPGA & CPLD |
| Estado del ciclo de vida | Última compra | NRND |
| Estado del stock | In Stock | In Stock |
| Precio unitario (USD) | $168,00 | $27,85 |
| Family | MAX 9000 | MAX 9000 (third-generation Multiple Array MatriX) |
| Architecture | Multiple Array MatriX (MAX) - 3rd generation | — |
| Usable Gates | 12,000 | 12,000 |
| Macrocells | 560 | 560 |
| Logic Array Blocks (LABs) | 16 | 35 |
| User I/Os | 212 | — |
| Internal Operating Frequency | 144.9 MHz | — |
| Pin-to-Pin Propagation Delay (tPD) | 10 ns (-10 speed grade) | 15 ns |
| Tensión de alimentación | 5.0 V | 5.0 V |
| Process Technology | 0.65 µm CMOS EEPROM | — |
| Encapsulado | 240-pin RQFP (Plastic Quad Flat Pack) | RQFP-240 (240-pin Plastic Quad Flat Pack) |
| Programming Interface | JTAG (IEEE 1149.1) - in-system programmable | — |
| I/O Standards Supported | 5.0 V TTL/CMOS, 3.3 V PCI-compatible | — |
| Operating Temperature (Commercial) | 0 °C to +70 °C | — |
| Lead-Free Finish (N suffix) | Yes (Pb-free) | — |
| Estado RoHS | ROHS3 Compliant (per fpgalink.com listing) | [DATA_NEEDED: RoHS compliance - older Altera RQFP part] |
| Nivel de sensibilidad a la humedad (MSL) | 3 (168 hours) | — |
| Series | — | MAX 9000 |
| Maximum User I/O Pins | — | 216 |
| Internal Counter Frequency (fCNT) | — | 145 MHz |
| Global Setup Time (tFSU) | — | [DATA_NEEDED: tFSU for -15 grade] |
| Clock-to-Output Time (tFCO) | — | [DATA_NEEDED: tFCO for -15 grade] |
| Logic Family | — | CMOS (EEPROM-based) |
| Programmability | — | In-system programmable (IEEE 1532/JTAG) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |
| Temperatura de funcionamiento | — | 0C to +70C (Commercial) |
| Tipo de montaje | — | Surface Mount |