EPM9560RC240-12 vs EPM9560RC240-15N Comparison
Detailed side-by-side comparison of EPM9560RC240-12 by Altera and EPM9560RC240-15N by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC240-12 | EPM9560RC240-15N |
|---|---|---|
| Brand | Altera | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Nrnd |
| Stock Status | In Stock | In Stock |
| Unit Price (USD) | $9.95 | $27.85 |
| Family | MAX 9000 (EPM9560) | MAX 9000 (third-generation Multiple Array MatriX) |
| Device Type | EE PLD / CPLD | β |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | β |
| User I/O Pins | 191 | β |
| Logic Array Blocks (LABs) | 20 | 35 |
| Maximum Propagation Delay (tPD) | 13.4 ns | β |
| Speed Grade | -12 (13.4 ns tPD) | β |
| Maximum Operating Frequency (estimated) | ~76 MHz registered | β |
| Core Supply Voltage (VCCINT) | 5 V | β |
| I/O Logic Levels | 3.3 V or 5 V (configurable) | β |
| Package | PQFP-240 (RC240) 0.500 mm pitch, gull-wing | RQFP-240 (240-pin Plastic Quad Flat Pack) |
| Mounting Type | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | β |
| Programming Interface | IEEE 1149.1 JTAG | β |
| Process Technology | CMOS | β |
| Operating Temperature | [DATA_NEEDED: operating temperature grade] | 0C to +70C (Commercial) |
| RoHS Status | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance - older Altera RQFP part] |
| Series | β | MAX 9000 |
| Usable Gates | β | 12,000 |
| Maximum User I/O Pins | β | 216 |
| Pin-to-Pin Propagation Delay (tPD) | β | 15 ns |
| Internal Counter Frequency (fCNT) | β | 145 MHz |
| Global Setup Time (tFSU) | β | [DATA_NEEDED: tFSU for -15 grade] |
| Clock-to-Output Time (tFCO) | β | [DATA_NEEDED: tFCO for -15 grade] |
| Supply Voltage | β | 5.0 V |
| Logic Family | β | CMOS (EEPROM-based) |
| Programmability | β | In-system programmable (IEEE 1532/JTAG) |
| Boundary-Scan Test | β | JTAG (IEEE 1149.1) |