EPM9560RC240-12 vs EPM9560RC240-15N Ikinahambing
Detalyadong pagkakahiwalay na pagkakahambing ng EPM9560RC240-12 sa pamamagitan ng Altera at EPM9560RC240-15N sa pamamagitan ng Altera. Ikinahambing ang mga pangunahing paglalarawan, mga tama ng elektriko, paakay, kalagayan ng buhay, presyo, at pagkakaroon upang makita ang pinakamahusay na komponente para sa iyong mga kinakailangang pang disenyo.
Pagsanggunian na paghahambing
| Parametro | EPM9560RC240-12 | EPM9560RC240-15N |
|---|---|---|
| Brand | Altera | Altera |
| Kategorya | FPGA & CPLD | FPGA & CPLD |
| Katayuan ng Lifecycle | Obsolete | NRND |
| Family | MAX 9000 (EPM9560) | MAX 9000 (third-generation Multiple Array MatriX) |
| Device Type | EE PLD / CPLD | — |
| Macrocells | 560 | 560 |
| Flip-Flops | 772 | — |
| User I/O Pins | 191 | — |
| Logic Array Blocks (LABs) | 20 | 35 |
| Maximum Propagation Delay (tPD) | 13.4 ns | — |
| Speed Grade | -12 (13.4 ns tPD) | — |
| Maximum Operating Frequency (estimated) | ~76 MHz registered | — |
| Core Supply Voltage (VCCINT) | 5 V | — |
| I/O Logic Levels | 3.3 V or 5 V (configurable) | — |
| Packhaging | PQFP-240 (RC240) 0.500 mm pitch, gull-wing | RQFP-240 (240-pin Plastic Quad Flat Pack) |
| Uri ng Pagpapasok | Surface Mount | Surface Mount |
| Configuration Memory | EEPROM (non-volatile) | — |
| Programming Interface | IEEE 1149.1 JTAG | — |
| Process Technology | CMOS | — |
| Temperature na Operasyon | [DATA_NEEDED: operating temperature grade] | 0C to +70C (Commercial) |
| Tindminan RoHS | [DATA_NEEDED: RoHS compliance] | [DATA_NEEDED: RoHS compliance - older Altera RQFP part] |
| Series | — | MAX 9000 |
| Usable Gates | — | 12,000 |
| Maximum User I/O Pins | — | 216 |
| Pin-to-Pin Propagation Delay (tPD) | — | 15 ns |
| Internal Counter Frequency (fCNT) | — | 145 MHz |
| Global Setup Time (tFSU) | — | [DATA_NEEDED: tFSU for -15 grade] |
| Clock-to-Output Time (tFCO) | — | [DATA_NEEDED: tFCO for -15 grade] |
| Volte ng Pagbibigay | — | 5.0 V |
| Logic Family | — | CMOS (EEPROM-based) |
| Programmability | — | In-system programmable (IEEE 1532/JTAG) |
| Boundary-Scan Test | — | JTAG (IEEE 1149.1) |