EPM9560RC28-15 vs EPM9560RC-10 Comparison
Detailed side-by-side comparison of EPM9560RC28-15 by Altera and EPM9560RC-10 by Intel. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Specification Comparison
| Parameter | EPM9560RC28-15 | EPM9560RC-10 |
|---|---|---|
| Brand | Altera | Intel |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | MAX 9000 |
| Logic Elements | 560 | — |
| Usable Gates | 6,000 | 12,000 |
| Macrocells | 212 | 560 |
| Logic Array Blocks (LABs) | 16 | 16 |
| Propagation Delay (tPD) | 15 ns | — |
| Supply Voltage (VCCINT) | 5.0 V | — |
| I/O Tolerance | 5.0 V (3.3 V with level shift) | — |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | IEEE 1149.1 JTAG |
| Configuration Memory | EEPROM (UV-erasable window on RC package) | — |
| Maximum User I/O (largest package) | 212 | — |
| Operating Temperature Range | -40C to +85C (industrial) / military options | — |
| Package | 28-pin ceramic windowed DIP (RC-28) | 240-pin PGA (RC suffix) |
| Mounting Type | Through-Hole (DIP) | Through-Hole / Socketed |
| RoHS Status | Non-compliant (ceramic windowed DIP, military/aerospace pedigree) | unknown |
| Device Type | — | CPLD (Complex Programmable Logic Device) |
| Maximum User I/O Pins | — | 212 |
| Pin-to-Pin Delay (tPD) | — | 10 ns |
| Supply Voltage (VCCINT/VCCIO) | — | 5.0 V |
| Process Technology | — | CMOS EEPROM |
| Architecture | — | Multiple Array Matrix (MAX) - third generation |
| Operating Temperature | — | 0C to +70C (commercial) |