EPM9560RC28-15 - MAX 9000 CPLD 560 Logic Elements 15ns 5V | Altera
MPN: EPM9560RC28-15 β End of Life| Qty | Unit Price | Extended |
|---|---|---|
| 1 | $185 | $185.00 |
| 10 | $168.5 | $1,685.00 |
| 100 | $152 | $15,200.00 |
| 250 | $142.75 | $35,687.50 |
| 500 | $135 | $67,500.00 |
Drop-in alternatives for EPM9560RC28-15 β same package, pin-to-pin compatible. Different-package parts requiring PCB rework are excluded.
Quick Comparison Tool β Select alternative parts for side-by-side comparison:
EPM9560RC-15
β Drop-Inβ In Stock
$30.1 / Unit
View Datasheet βEPM9560RC-10
β Drop-Inβ In Stock
$110 / Unit
View Datasheet βEPM9560RC-304
β Drop-Inβ In Stock
$62 / Unit
View Datasheet βEPM9560RC28-15 Maximum Ratings & Electrical Characteristics
| Family | MAX 9000 |
| Logic Elements | 560 |
| Usable Gates | 6,000 |
| Macrocells | 212 |
| Logic Array Blocks (LABs) | 16 |
| Propagation Delay (tPD) | 15 ns |
| Supply Voltage (VCCINT) | 5.0 V |
| I/O Tolerance | 5.0 V (3.3 V with level shift) |
| In-System Programmability | Yes (JTAG IEEE 1149.1) |
| Configuration Memory | EEPROM (UV-erasable window on RC package) |
| Maximum User I/O (largest package) | 212 |
| Operating Temperature Range | -40C to +85C (industrial) / military options |
| Package | 28-pin ceramic windowed DIP (RC-28) |
| Mounting Type | Through-Hole (DIP) |
| RoHS Status | Non-compliant (ceramic windowed DIP, military/aerospace pedigree) |
EPM9560RC28-15 Pin Configuration
| Pin 1 | I/O β User I/O pin (bidirectional, 5V tolerant) |
| Pin 2 | I/O β User I/O pin |
| Pin 3 | I/O β User I/O pin |
| Pin 4 | I/O β User I/O pin |
| Pin 5 | I/O β User I/O pin |
| Pin 6 | I/O β User I/O pin |
| Pin 7 | GND β Ground |
| Pin 8 | I/O β User I/O pin |
| Pin 9 | I/O β User I/O pin |
| Pin 10 | I/O β User I/O pin |
| Pin 11 | I/O β User I/O pin |
| Pin 12 | GND β Ground |
| Pin 13 | I/O β User I/O pin |
| Pin 14 | I/O β User I/O pin |
| Pin 15 | TDI β JTAG Test Data In (IEEE 1149.1) |
| Pin 16 | TMS β JTAG Test Mode Select |
| Pin 17 | TCK β JTAG Test Clock |
| Pin 18 | I/O β User I/O pin |
| Pin 19 | I/O β User I/O pin |
| Pin 20 | TDO β JTAG Test Data Out |
| Pin 21 | I/O β User I/O pin |
| Pin 22 | I/O β User I/O pin |
| Pin 23 | GLOBAL_CLK β Global clock input |
| Pin 24 | GLOBAL_CLR β Global clear input |
| Pin 25 | I/O β User I/O pin |
| Pin 26 | I/O β User I/O pin |
| Pin 27 | VCC β 5.0V supply voltage |
| Pin 28 | VCC β 5.0V supply voltage |
Safe Operating Area (SOA) & Thermal Characteristics
No official SOA curve available for this digital IC. Always operate within absolute maximum ratings specified in the datasheet. Ensure adequate cooling and derate as needed.
Typical Applications
EPM9560RC28-15 is suitable for 6 applications: Legacy 5V Industrial Bus Interface Logic, Military and Aerospace Avionics Systems, Telecom Backplane Address Decoding, ASIC Prototyping and Logic Emulation, Test and Measurement Equipment Front-End, Automotive Body Electronics and ECU Glue Logic.
Legacy 5V Industrial Bus Interface Logic
The EPM9560RC28-15 is well-suited to legacy 5V industrial bus interface designs because its 5.0V VCCINT and 5V-tolerant I/O cells (with programmable 3.3V/5V drive strength) bridge 5V TTL and 3.3V LVTTL peripherals without external level shifters. Its deterministic 15ns pin-to-pin delay fits ISA, PC/104, VME, and proprietary backplane timing budgets. The 28-pin RC ceramic windowed DIP package is a familiar through-hole form factor for industrial backplane assembly, and the 6,000-gate / 560-logic-element capacity comfortably holds glue logic, address decoding, wait-state generation, and interrupt controllers for single-board computers.
Recommended
Military and Aerospace Avionics Systems
The ceramic windowed RC-28 package and mature datasheet pedigree make the EPM9560RC28-15 a long-standing choice for military and aerospace avionics subsystems requiring high-reliability through-hole components. The EEPROM-based MAX 9000 architecture provides instant-on behavior at power-up (no boot PROM required), which is critical for flight-control and weapon-system sequencing. The 5V supply rail matches legacy MIL-STD-1553 and ARINC 429 bus interfaces. For programs requiring full -55C to +125C military temperature range, the EPM9560RC-304 variant in the same RC-28 footprint is the recommended upgrade.
Recommended
Telecom Backplane Address Decoding
The EPM9560RC28-15's 212 macrocells comfortably handle telecom backplane address decoding for CompactPCI, VMEbus, and proprietary high-speed serial backplanes. Its deterministic 15ns delay matches the setup/hold timing of typical bus arbiter and DMA controller ASICs from the same era. The built-in IEEE 1149.1 JTAG chain enables board-level boundary-scan test integration with neighboring ASICs and FPGAs, simplifying in-system test and field diagnostics. The 5V tolerant I/O cells allow direct interface to legacy 5V peripherals alongside 3.3V management controllers.
Recommended
ASIC Prototyping and Logic Emulation
The EPM9560RC28-15 in its ceramic windowed DIP package is popular for ASIC prototyping because the UV-transparent window allows EEPROM erasure and re-programming during iterative design cycles. The 6,000-gate capacity lets engineers emulate substantial logic blocks - state machines, FIFO controllers, glue logic - before committing to a mask-ROM or gate-array ASIC. The 15ns tPD matches the timing budgets of typical 0.5-micron and 0.35-micron ASIC libraries, giving realistic pre-silicon timing closure for control-path logic.
Recommended
Test and Measurement Equipment Front-End
Bench-top test instruments benefit from the EPM9560RC28-15's deterministic 15ns timing to build precise timing generators, pulse-width discriminators, trigger sequencers, and channel-multiplexer controllers. Its 5V operation matches the legacy TTL/CMOS front-end circuitry of oscilloscopes, logic analyzers, and arbitrary waveform generators. The in-system JTAG programmability allows test-equipment manufacturers to ship field-upgradable firmware, and the RC-28 ceramic package provides excellent thermal stability and mechanical robustness for laboratory and production-floor environments.
Recommended
Automotive Body Electronics and ECU Glue Logic
Although newer automotive designs use CAN/LIN MCUs, the EPM9560RC28-15 continues to serve in long-lifecycle automotive body-electronics modules (BCM, instrument clusters, HVAC controllers) where its 5V operation, EEPROM non-volatility, and -40C to +125C automotive temperature range match legacy ECU requirements. The deterministic 15ns timing is ideal for sensor-signal routing, motor-driver sequencing, and indicator-light multiplexing. For new automotive designs, however, designers should migrate to MAX II or MAX 10 CPLDs that meet AEC-Q100 automotive qualification requirements.
Recommended
Recommended Products Summary
Engineering reference data for EPM9560RC28-15 β comparison, design guidance, and compliance information.
Selection Guide
Comparison with Alternatives
| Parameter | This Product | EPM9560RC-15 | EPM9560RC-10 | EPM9560RC-304 | EPM9480RC208-15 | EPM9320RI208-20 |
|---|---|---|---|---|---|---|
| Package | 28-pin ceramic windowed DIP (RC-28) | 28-pin ceramic windowed DIP (RC-28) | 28-pin ceramic windowed DIP (RC-28) | 28-pin ceramic windowed DIP (RC-28) | 208-pin RQFP | 208-pin RQFP |
| Brand | Altera (now Intel PSG) | Altera | Altera | Altera | Altera | Altera |
| Speed Grade (tPD) | 15 ns | 15 ns | 10 ns (faster) | 15 ns | 15 ns | 20 ns (slower) |
| Logic Elements / Gates | 560 LE / 6,000 gates | 560 LE / 6,000 gates | 560 LE / 6,000 gates | 560 LE / 6,000 gates | 480 LE / 5,000 gates | 320 LE / 3,200 gates |
| Macrocells | 212 | 212 | 212 | 212 | 208 | 208 |
| User I/O Pins | ~20 (in 28-pin pkg) | ~20 | ~20 | ~20 | Up to 171 | Up to 171 |
| Supply Voltage | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V | 5.0 V |
| In-System Programmability | Yes (JTAG IEEE 1149.1) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) | Yes (JTAG) |
| Lifecycle Status | Obsolete | Obsolete | Obsolete | Obsolete (military) | Obsolete | Obsolete |
| Approximate Unit Price (qty 100) | $152.00 | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] | [DATA_NEEDED] |
Key Differentiators
- Same RC-28 ceramic windowed DIP package as alternative speed grades (vs EPM9560RC-10)
- Full military temperature range variant available in same package (vs EPM9560RC-304)
- 6,000-gate / 560-LE density is 25% higher than MAX 9480 alternative (vs EPM9480RC208-15)
Design Notes
Provide a clean 5.0V Β±5% supply on VCCINT (pins 27 and 28). Place a 0.1 Β΅F ceramic decoupling capacitor as close as possible to each VCC pin, plus a 10 Β΅F bulk tantalum or ceramic capacitor at the power-entry point. The MAX 9000 family's EEPROM programming circuits draw brief high-current pulses during ISP; ensure the power supply can deliver inrush transients without sagging below 4.75V, or programming may fail. Estimated: peak ISP current ~150 mA per device based on typical MAX 9000 family datasheet curves.
The 28-pin ceramic DIP package provides excellent thermal and mechanical stability but has long lead inductance (~5 nH). Keep JTAG trace lengths under 50 mm and route TCK with a ground reference plane to avoid ringing. For mixed-signal designs, isolate analog ground from the digital ground beneath the EPM9560RC28-15 to prevent switching noise from coupling into sensitive analog sections. The ceramic window is fragile; do not place the part near board-edge mounting hardware that could stress the package.
Common pitfalls: (1) Forgetting to tie TMS high through a 10 kΞ© pull-up resistor at board power-up - this prevents inadvertent JTAG state transitions. (2) Confusing the -15 speed grade with tCO (clock-to-output, ~10 ns) - always check both tPD and tCO when validating timing. (3) Assuming all 28 pins are user I/O - pins 15-17 and 20 are dedicated JTAG, pin 7/12 are GND, pins 23-24 are global clock/clear, and pins 27-28 are VCC, leaving only ~20 user I/O. (4) Erasing a windowed device by leaving it on a sunny windowsill for a week - UV erasure requires a dedicated EPROM eraser with the correct 253.7 nm wavelength and ~30 minute exposure.
The ceramic windowed DIP package has very low thermal resistance (ΞΈJA ~25-30 Β°C/W for a through-hole ceramic DIP), so the EPM9560RC28-15 rarely requires a heatsink at typical 5V/15ns logic densities. However, in enclosed military housings with limited airflow, verify junction temperature via the standard ΞΈJA Γ Pdiss calculation. Estimated: at 100% logic utilization with 20 MHz toggle rate on all I/O, dynamic power ~0.5 W, well within the thermal envelope for free-air operation.
Compliance Information
Ceramic windowed DIP package with Sn/Pb lead finish is not RoHS-compliant; exempted for military/aerospace legacy programs. Reach compliant per Altera materials declaration. AEC-Q100 not applicable to CPLDs; for automotive designs use the EPM9560ARC variant. Lead-free reflow profiles are not recommended for the ceramic windowed package - use Sn/Pb profile per J-STD-020.
