EPM9560RC304-2 vs EPM9560RC304-15 Comparison
Detailed side-by-side comparison of EPM9560RC304-2 by Intel and EPM9560RC304-15 by Altera. Compare key specifications, electrical parameters, packaging, lifecycle status, pricing, and availability to determine the best component for your design requirements.
Intel
EPM9560RC304-2 - MAX 9000 EPLD 12k Gates 304-pin RQFP | Intel / Altera
EPM9560RC304-2 ObsoleteSpecification Comparison
| Parameter | EPM9560RC304-2 | EPM9560RC304-15 |
|---|---|---|
| Brand | Intel | Altera |
| Category | FPGA & CPLD | FPGA & CPLD |
| Lifecycle Status | Obsolete | Obsolete |
| Family | MAX 9000 | — |
| Device Type | CPLD (EPLD - Erasable PLD) | — |
| Usable Gates | Approximately 12,000 | — |
| Logic Array Blocks (LABs) | 16 | 16 |
| Macrocells | [DATA_NEEDED: macrocell count] | 560 |
| User I/O Pins | 304 | 212 (maximum) |
| Package | 304-pin RQFP (RC) | 304-pin RQFP (Plastic Quad Flat Pack) |
| Speed Grade | -2 | — |
| Core Supply Voltage | 5.0 V | — |
| I/O Supply Voltage | 5.0 V | — |
| Programming Technology | EEPROM (in-system programmable) | — |
| JTAG Support | IEEE Std. 1149.1 (boundary-scan + ISP) | — |
| Operating Temperature | Commercial (0C to +70C) | [DATA_NEEDED: industrial/commercial temperature grade] |
| Mounting Type | Surface Mount | Surface Mount |
| RoHS Status | [DATA_NEEDED: RoHS compliance status] | [DATA_NEEDED: lead-free / RoHS compliance status] |
| Lead-Free | [DATA_NEEDED: lead-free status] | — |
| Architecture | Multiple Array MatriX (MAX) - third generation | Multiple Array MatriX (MAX), EEPROM-based |
| Configuration Memory | On-chip EEPROM (non-volatile) | On-chip EEPROM (non-volatile) |
| Device Family | — | MAX 9000 |
| Propagation Delay (tPD) | — | 15 ns (combinatorial, pin-to-pin) |
| Pin Count | — | 304 |
| Supply Voltage (VCCINT) | — | 5.0 V |
| I/O Standard | — | 5.0 V TTL / PCI-compliant |
| In-System Programmability | — | Yes, via IEEE Std. 1149.1 JTAG |
| Technology Node | — | High-performance CMOS, EEPROM process |